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ADS1281IPWRG4 Datasheet(PDF) 3 Page - Texas Instruments |
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ADS1281IPWRG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 51 page ADS1281 www.ti.com SBAS378D – AUGUST 2007 – REVISED JUNE 2010 ELECTRICAL CHARACTERISTICS Limit specifications at –40°C to +85°C, typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK (1) = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, and fDATA = 1000SPS, unless otherwise noted. ADS1281 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage VIN = AINP – AINN ±VREF/2 V Absolute input range AINP or AINN AVSS – 0.1 AVDD + 0.1 V Differential input impedance 55 k Ω AC PERFORMANCE fDATA = 250SPS 130 fDATA = 500SPS 127 Signal-to-noise ratio(2) SNR fDATA = 1000SPS 120 124 dB fDATA = 2000SPS 121 fDATA = 4000SPS 118 Total harmonic distortion THD –122 –115 dB VIN = 31.25Hz, –0.5dBFS Spurious-free dynamic SFDR 123 dB range(3) DC PERFORMANCE Resolution No missing codes 31 Bits FIR filter mode 250 4000 SPS Data rate fDATA Sinc filter mode 8,000 128,000 SPS Integral nonlinearity(4) INL Differential input 0.00006 0.0005 % FSR(5) Offset error 10 200 mV Offset error after calibration(6) Shorted input 1 mV Offset drift 0.06 mV/°C Gain error 0.1 0.3 % Gain error after calibration(6) 0.0002 % Gain drift 0.4 ppm/°C Common-mode rejection fCM = 60Hz 105 120 dB AVDD, AVSS 85 95 Power-supply rejection fPS = 60Hz dB DVDD 85 105 FIR DIGITAL FILTER RESPONSE Passband ripple ±0.003 dB Passband (–0.01dB) 0.375 × fDATA Hz Stop band attenuation(7) 135 dB Stop band 0.500 × fDATA Hz Bandwidth (–3dB) 0.413 × fDATA Hz FIR filter, minimum phase(8) 5/fDATA Group delay s FIR filter, linear phase 31/fDATA FIR filter, minimum phase 62/fDATA Settling time (latency) s FIR filter, linear phase 62/fDATA High-pass filter corner 0.1 10 Hz (1) fCLK = system clock. (2) SNR = signal-to-noise ratio = 20 log (VRMS Full-Scale/VRMS Noise), VIN = 20mVDC. (3) Highest spurious component including harmonics. (4) Best-fit method. (5) FSR: Full-scale range = ±VREF/2. (6) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings). (7) Input frequencies in the range of NfCLK/512 ± fDATA/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency ranges intermodulation = 120dB, typ. (8) At dc; see Figure 32. Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): ADS1281 |
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