 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ADS1672IPAGR Datasheet(PDF) 7 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
ADS1672IPAGR Datasheet(HTML) 7 Page - Texas Instruments |
|
|
7 / 34 page  CLK DRDY t CLK t SCLK SCLK internal t DRPW t CLKDR t DOPD t DOHD t DRSCLK DOUT MSB LSB ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 TIMING CHARACTERISTICS Figure 1. Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0) TIMING REQUIREMENTS: Internal SCLK At TA = –40°C to +85°C, and DVDD = 2.7V to 3.3V. SYMBOL DESCRIPTION MIN TYP MAX UNIT tCLK CLK period (1/fCLK) 50 ns tCLKDR CLK to DRDY delay 36 ns tDRPW DRDY pulse width 1 tCLK tDRSCLK Internally-generated SCLK rising edge to DRDY rising edge 4 ns tSCLK SCLK period (1/fSCLK) 1 tCLK tDOPD Rising edge of SCLK to new valid data output (propagation delay) 3 ns tDC CLK duty cycle 45 55 % tSPWH SCLK pulse width high 20 ns Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS1672 |
Número de pieza similar - ADS1672IPAGR |
|
Descripción similar - ADS1672IPAGR |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
