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TLC2578IPWR Datasheet(PDF) 3 Page - Texas Instruments

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No. de pieza TLC2578IPWR
Descripción Electrónicos  14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TLC2578IPWR Datasheet(HTML) 3 Page - Texas Instruments

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TLC3574, TLC3578, TLC2574, TLC2578
5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL
SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
3
WWW.TI.COM
equivalent input circuit
Equivalent Digital Input Circuit
Digital Input
VDD
3.94 k
6.6 k
9.9 k
Bipolar Signal Scaling
1.5 k
Ron
MUX
C(sample)= 30 pF
REFP
REFM
Ain
Diode Turn on Voltage: 35 V
Equivalent Analog Input Circuit
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
TLC3574
TLC2574
TLC3578
TLC2578
I/O
DESCRIPTION
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
9
10
11
12
9
10
11
12
13
14
15
16
I
Analog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The
driving source impedance should be less than or equal to 25
Ω for normal sampling. For larger
source impedance, use the external hardware conversion start signal CSTART (the low time of
CSTART controls the sampling period) or reduce the frequency of SCLK to increase the sampling
time.
AGND
14, 18
18, 22
I
Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage
measurements are with respect to AGND.
AVDD
13, 19
17, 23
I
Analog supply voltage
COMP
17
21
I
Internal compensation pin. Install compensation capacitors 0.1
µF between this pin and AGND.
CS
8
8
I
Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is
disabled to clock data, but works as conversion clock source if programmed. The falling edge of
CS input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from
high-impedance state.
If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave
select (SS) to provide an SPI interface.
If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip
select to allow host to access the individual converter.
CSTART
20
24
I
External sampling trigger signal, which initiates the sampling from a selected analog input channel
when the device works in extended sampling mode (asynchronous sampling). A high-to-low
transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold
mode and starts the conversion. The low time of the CSTART signal controls the sampling period.
CSTART signal must stay low long enough for proper sampling. CSTART must stay high long
enough after the low-to-high transition for the conversion to finish maturely. The activation of
CSTART is independent of SCLK and the level of CS and FS. However, the first CSTART cannot
be issued before the rising edge of the eleventh SCLK. Tie this pin to DVDD if not used.
DGND
6
6
I
Digital ground return for the internal circuitry
DVDD
7
7
I
Digital supply voltage


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