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ADC78H90CIMTX Datasheet(PDF) 5 Page - Texas Instruments |
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ADC78H90CIMTX Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 24 page  ADC78H90 www.ti.com SNAS227D – NOVEMBER 2003 – REVISED MARCH 2013 ADC78H90 Converter Electrical Characteristics (1) (continued) The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500 KSPS, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Limits Symbol Parameter Conditions Typical Units (2) POWER SUPPLY CHARACTERISTICS (CL = 10 pF) 2.7 V (min) AVDD, Analog and Digital Supply Voltages AVDD ≥ DVDD DVDD 5.25 V (max) AVDD = DVDD = +4.75V to +5.25V, 1.65 2.3 mA (max) fSAMPLE = 500 kSPS, fIN = 40 kHz Total Supply Current, Normal Mode (Operational, CS low) AVDD = DVDD = +2.7V to +3.6V, 0.5 2.3 mA (max) fSAMPLE = 500 kSPS, fIN = 40 kHz IA + ID AVDD = DVDD = +4.75V to +5.25V, 200 nA fSAMPLE = 0 kSPS Total Supply Current, Shutdown (CS high) AVDD = DVDD = +2.7V to +3.6V, 200 nA fSAMPLE = 0 kSPS \AVDD = DVDD = +4.75V to +5.25V 8.3 12 mW (max) Power Consumption, Normal Mode (Operational, CS low) AVDD = DVDD = +2.7V to +3.6V 1.5 8.3 mW (max) PD AVDD = DVDD = +4.75V to +5.25V 0.5 µW Power Consumption, Shutdown (CS high) AVDD = DVDD = +2.7V to +3.6V 0.3 µW AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency 8 MHz (min) fSMIN Minimum Clock Frequency 50 kHz fS Maximum Sample Rate 500 KSPS (min) tCONV Conversion Time 13 SCLK cycles 40 % (min) DC SCLK Duty Cycle 50 60 % (max) tACQ Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles fRATE Throughput Rate 500 kSPS (min) tAD Aperture Delay 4 ns ADC78H90 Timing Specifications The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500 KSPS, CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Limits Symbol Parameter Conditions Typical Units (1) Setup Time SCLK High to CS Falling t1a (2) 10 ns (min) Edge Hold time SCLK Low to CS Falling t1b (2) 10 ns (min) Edge t2 Delay from CS Until DOUT active 30 ns (max) Data Access Time after SCLK Falling t3 30 ns (max) Edge Data Setup Time Prior to SCLK Rising t4 10 ns (min) Edge t5 Data Valid SCLK Hold Time 10 ns (min) t6 SCLK High Pulse Width 0.4 x tSCLK ns (min) t7 SCLK Low Pulse Width 0.4 x tSCLK ns (min) CS Rising Edge to DOUT High- t8 20 ns (max) Impedance (1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level). (2) Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t1a and t1b. Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC78H90 |
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