ADC104S021 datasheet(6/28 Pages) TI1

No. de pieza	ADC104S021

Descripción Electrónicos	ADC104S101 4 Channel, 500 ksps to 1 Msps, 10-Bit A/D Converter

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Fabricante Electrónico	TI1 [Texas Instruments]

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ADC104S101

SNAS284F – FEBRUARY 2005 – REVISED MARCH 2013

www.ti.com

ADC104S101 Timing Specifications

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500

ksps to 1 Msps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Parameter

Test Conditions

Typical

Limits(1)

Units

VA = +3.0V

−3.5

tCSU

Setup Time SCLK High to CS Falling Edge

See(2)

10

ns (min)

VA = +5.0V

−0.5

VA = +3.0V

+4.5

tCLH

Hold time SCLK Low to CS Falling Edge

See(2)

10

ns (min)

VA = +5.0V

+1.5

VA = +3.0V

+4

tEN

Delay from CS Until DOUT active

30

ns (max)

VA = +5.0V

+2

VA = +3.0V

+16.5

tACC

Data Access Time after SCLK Falling Edge

30

ns (max)

VA = +5.0V

+15

tSU

Data Setup Time Prior to SCLK Rising Edge

+3

10

ns (min)

tH

Data Valid SCLK Hold Time

+3

10

ns (min)

tCH

SCLK High Pulse Width

0.5 x tSCLK 0.3 x tSCLK

ns (min)

tCL

SCLK Low Pulse Width

0.5 x tSCLK 0.3 x tSCLK

ns (min)

VA = +3.0V

1.7

Output Falling

VA = +5.0V

1.2

tDIS

CS Rising Edge to DOUT High-Impedance

20

ns (max)

VA = +3.0V

1.0

Output Rising

VA = +5.0V

1.0

(1)

Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(2)

Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.

6

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