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74ACT139 Datasheet(PDF) 3 Page - Hitachi Semiconductor |
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74ACT139 Datasheet(HTML) 3 Page - Hitachi Semiconductor |
3 / 10 page HD74AC139/HD74ACT139 3 Logic Diagram O3b O2b O1b O0b O3a O2a O1a O0a Ea Eb A0a A1a A0b A1b Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Functional Description The HD74AC139/HD74ACT139 is a high-speed dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each of which accepts two binary weighted inputs (A 0 to A1) and provides four mutually exclusive active-Low outputs ( O 0 to O3). Each decoder has an active-Low enable (E). When E is High all outputs are forced High. The enable can be used as the data input for a 4-output demultiplexer application. Each half of the HD74AC139/HD74ACT139 generates all four minterms of two variables. These four minterms are useful in some applications, replacing multiple gate functions as shown in Figure a, and thereby reducing the number of packages required in a logic network. Truth Table Inputs Outputs E A 0 A 1 O 0 O 1 O 2 O 3 H X X HHH H LL L L H H H LH L H L H H L L H HHL H L H H HHH L H : High Voltage Level L : Low Voltage Level X : Immaterial |
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