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GMS81C2112 Datasheet(PDF) 75 Page - Hynix Semiconductor

No. de Pieza. GMS81C2112
Descripción  HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
Descarga  107 Pages
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Fabricante  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/ko/index.jsp
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GMS81C2112 Datasheet(HTML) 75 Page - Hynix Semiconductor

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GMS81C2112/GMS81C2120
JUNE. 2001 Ver 1.00
69
16.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.
Figure 16-6 Execution of Multi Interrupt
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.
Example: During Timer1 interrupt is in progress, INT0 in-
terrupt serviced without any suspend.
TIMER1:
PUSH
A
PUSH
X
PUSH
Y
LDM
IENH,#80H
;
Enable INT0 only
LDM
IENL,#0
;
Disable other
EI
;
Enable Interrupt
:
:
:
:
:
:
LDM
IENH,#0F0H
;
Enable all interrupts
LDM
IENL,#0F0H
POP
Y
POP
X
POP
A
RETI
enable INT0
TIMER 1
service
INT0
service
Main Program
service
Occur
TIMER1 interrupt
Occur
INT0
EI
disable other
enable INT0
enable other
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.


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