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GMS81C2112 Datasheet(PDF) 76 Page - Hynix Semiconductor

No. de Pieza. GMS81C2112
Descripción  HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
Descarga  107 Pages
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Fabricante  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/ko/index.jsp
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GMS81C2112 Datasheet(HTML) 76 Page - Hynix Semiconductor

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GMS81C2112/GMS81C2120
70
JUNE. 2001 Ver 1.00
16.4 External Interrupt
The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0F8H) as shown in Figure 16-7.
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
Figure 16-7 External Interrupt Block Diagram
INT0 and INT1 are multiplexed with general I/O ports
(R00 and R01). To use as an external interrupt pin, the bit
of R4 port mode register R0FUNC should be set to “1” cor-
respondingly.
Example: To use as an INT0 and INT1
:
:
;
**** Set port as an input port R00,R01
LDM
R0IO,#1111_1100B
;
;
**** Set port as an interrupt port
LDM
R0FUNC,#0000_0011B
;
;
**** Set Falling-edge Detection
LDM
IEDS,#0000_0101B
:
:
:
Response Time
The INT0 and INT1 edge are latched into INT0IF and
INT1IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a re-
quest is active and conditions are right for it to be acknowl-
edged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.
Figure 16-8shows interrupt response timings.
Figure 16-8 Interrupt Response Timing Diagram
INT1IF
INT1 pin
INT1 INTERRUPT
IEDS
[0E6H]
INT0IF
INT0 pin
INT0 INTERRUPT
Edge selection
Register
2
2
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
8 fXIN
max. 12 fXIN


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