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GMS81C2112 Datasheet(PDF) 80 Page - Hynix Semiconductor

No. de Pieza. GMS81C2112
Descripción  HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
Descarga  107 Pages
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Fabricante  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/ko/index.jsp
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GMS81C2112 Datasheet(HTML) 80 Page - Hynix Semiconductor

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GMS81C2112/GMS81C2120
74
JUNE. 2001 Ver 1.00
17.2 Stop Mode
In the Stop mode, the on-chip oscillator is stopped. With
the clock frozen, all functions are stopped, but the on-chip
RAM and Control registers are held. The port pins out the
values held by their respective port data register, port di-
rection registers. Oscillator stops and the systems internal
operations are all held up.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
• The program counter stop the address of the
instruction to be executed after the instruction
"STOP" which starts the STOP operating mode.
The Stop mode is activated by execution of STOP in-
struction after clearing the bit WAKEUP of CKCTLR
to “0”. (This register should be written by byte opera-
tion. If this register is set by bit manipulation instruc-
tion, for example "set1" or "clr1" instruction, it may
be undesired operation)
In the Stop mode of operation, VDD can be reduced to min-
imize power consumption. Care must be taken, however,
to ensure that VDD is not reduced before the Stop mode is
invoked, and that VDD is restored to its normal operating
level, before the Stop mode is terminated.
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
Note: After STOP instruction, at least two or more NOP in-
struction should be written
Ex)
LDM CKCTLR,#0000_1110B
STOP
NOP
NOP
In the STOP operation, the dissipation of the power asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
of the STOP feature. This point should be little current
flows when the input level is stable at the power voltage
level (VDD/VSS); however, when the input level gets high-
er than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal into the
high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other
means.
Release the STOP mode
The exit from STOP mode is hardware reset or external in-
terrupt. Reset re-defines all the Control registers but does
not change the on-chip RAM. External interrupts allow
both on-chip RAM and Control registers to retain their val-
ues.
If I-flag = 1, the normal interrupt response takes place. If I-
flag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine. (refer to Figure 17-1)
When exit from Stop mode by external interrupt, enough
oscillation stabilization time is required to normal opera-
tion. Figure 17-2 shows the timing diagram. When release
the Stop mode, the Basic interval timer is activated on
wake-up. It is increased from 00H until FFH. The count
overflow is set to start normal operation. Therefore, before
STOP instruction, user must be set its relevant prescaler di-
vide ratio to have long enough time (more than 20msec).
This guarantees that oscillator has started and stabilized.
By reset, exit from Stop mode is shown in Figure .
Figure 17-1 STOP Releasing Flow by Interrupts
IEXX
=0
=1
STOP
INSTRUCTION
STOP Mode
Interrupt Request
STOP Mode Release
I-FLAG
=1
Interrupt Service Routine
Next
INSTRUCTION
=0
Master Interrupt
Enable Bit PSW[2]
Corresponding Interrupt
Enable Bit (IENH, IENL)


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