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GMS81C2112 Datasheet(PDF) 87 Page - Hynix Semiconductor |
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GMS81C2112 Datasheet(HTML) 87 Page - Hynix Semiconductor |
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87 / 107 page 
GMS81C2112/GMS81C2120 JUNE. 2001 Ver 1.00 81 20. POWER FAIL PROCESSOR The GMS81C21xx has an on-chip power fail detection cir- cuitry to immunize against power noise. A configuration register, PFDR, can enable or disable the power fail detect circuitry. Whenever VDD falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze MCU according to PFDM bit of PFDR. Refer to “7.4 DC Electrical Characteristics for Standard Pins(5V)” on page 14. In the in-circuit emulator, power fail function is not imple- mented and user can not experiment with it. Therefore, af- ter final development of user program, this function may be experimented or evaluated. Note: User can select power fail voltage level according to PFD0, PFD1 bit of CONFIG register(703FH) at the OTP (GMS87C21xx) but must select the power fail voltage level to define PFD option of “Mask Order & Verification Sheet” at the mask chip(GMS81C21xx). Because the power fail voltage level of mask chip (GMS81C21xx) is determined according to mask option. Note: If power fail voltage is selected to 3.0V on 3V oper- ation, MCU is freezed at all the times. Table 20-1 Power fail processor . Figure 20-1 Power Fail Voltage Detector Register Power FailFunction OTP MASK Enable/Disable PFDIS flag PFDIS flag Level Selection PFS0 bit PFS1 bit Mask option PFDM 7 6543210 PFS INITIAL VALUE: ---- -100B ADDRESS: 0EFH PFDR R/W R/W R/W PFDIS Operation Mode 0 : Normal operation regardless of power fail 1 : MCU will be reset by power fail detection Disable Flag 0: Power fail detection enable 1: Power fail detection disable Power Fail Status 0: Normal operate 1: Set to “1” if power fail is detected |
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