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GMS81C2112 Datasheet(PDF) 93 Page - Hynix Semiconductor |
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GMS81C2112 Datasheet(HTML) 93 Page - Hynix Semiconductor |
93 / 107 page ![]() GMS81C2112/GMS81C2120 JUNE. 2001 Ver 1.00 87 Figure 21-5 Programming Flow Chart EPROM Enable Delay Time after THLD1 TDLY1 200 nS EPROM Enable Hold Time in Write Mode THLD2 100 nS EPROM Enable Delay Time after THLD2 TDLY2 200 nS CTL2,1 Setup Time after Low Address input and Data input TCD1 100 nS CTL1 Setup Time before Data output in Read and Verify Mode TCD2 100 nS Table 21-2 AC/DC Requirements for Program/Read Mode START Set VDD=VDD1H Set VPP=VIHP Verify blank First Address Location EPROM Write N=1 Verify Last address Apply 3x program cycle 100uS program time Next address location N Report Programming failure Verify of all address VDD=6V & 2.7V Report Verify failure Report Programming OK VDD=0V END FAIL PASS PASS YES FAIL NO FAIL YES PASS VPP=0V ? Verify N=N+1 NO |