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GMS81C2112 Datasheet(PDF) 27 Page - Hynix Semiconductor |
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GMS81C2112 Datasheet(HTML) 27 Page - Hynix Semiconductor |
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27 / 107 page 
GMS81C2112/GMS81C2120 JUNE. 2001 Ver 1.00 21 Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All inter- rupts are disabled when cleared to “0”. This flag immedi- ately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector ad- dress. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned 100H to 1FFH. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction ex- ceeds +127(7FH) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. When the BIT in- struction is executed, bit 7 of memory is copied to this flag. N NEGATIVE FLAG V G B H I Z C MSB LSB RESET VALUE : 00H PSW OVERFLOW FLAG BRK FLAG CARRY FLAG RECEIVES ZERO FLAG INTERRUPT ENABLE FLAG CARRY OUT HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS SELECT DIRECT PAGE when G=1, page is selected to “page 1” |
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