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GMS81C2112 Datasheet(PDF) 46 Page - Hynix Semiconductor |
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GMS81C2112 Datasheet(HTML) 46 Page - Hynix Semiconductor |
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46 / 107 page 
GMS81C2112/GMS81C2120 40 JUNE. 2001 Ver 1.00 Watchdog Timer Control Figure 11-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected during setting of the de- tection time, selecting of output, and clearing of the binary counter. Clearing the binary counter is repeated within the detection time. If the malfunction occurs for any cause, the watchdog tim- er output will become active at the rising overflow from the binary counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET pin to low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (WDTIF) is generated. The watchdog timer temporarily stops counting in the STOP mode, and when the STOP mode is released, it au- tomatically restarts (continues counting). Figure 11-2 WDTR: Watchdog Timer Data Register Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz 7 6543210 Clear count flag 0: Free-run count INITIAL VALUE: 0111_1111B ADDRESS: 0EDH WDTR WW W W 1: When the WDTCL is set to "1", binary counter is cleared to “0”. And the WDTCL becomes “0” automatically after one machine cycle. Counter count up again. 7-bit compare data W WWW NOTE: The WDTON bit is in register CKCTLR. WDTCL LDM CKCTLR,#3FH ; Select 1/2048 clock source, WDTON ← 1, Clear Counter LDM WDTR,#04FH LDM WDTR,#04FH ; Clear counter : : : : LDM WDTR,#04FH ; Clear counter : : : : LDM WDTR,#04FH ; Clear counter Within WDT detection time Within WDT detection time |
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