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GMS81C2112 Datasheet(PDF) 47 Page - Hynix Semiconductor

No. de Pieza. GMS81C2112
Descripción  HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
Descarga  107 Pages
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Fabricante  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/ko/index.jsp
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GMS81C2112 Datasheet(HTML) 47 Page - Hynix Semiconductor

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GMS81C2112/GMS81C2120
JUNE. 2001 Ver 1.00
41
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 4 in
CKCTLR) to “1”. WDTON is initialized to “0” during re-
set and it should be set to “1” to operate after reset is re-
leased.
Example: Enables watchdog timer for Reset
:
LDM
CKCTLR,#xx1x_xxxxB;WDTON
← 1
:
:
The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is re-
leased.
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 7-bit tim-
er by clearing bit5 of CKCTLR to “0”. The interval of
watchdog timer interrupt is decided by Basic Interval Tim-
er. Interval equation is shown as below.
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 7-bit timer interrupt set up.
LDM
CKCTLR,#xx0xxxxxB;WDTON
←0
LDM
WDTR,#7FH
;WDTCL
←1
:
Figure 11-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is gen-
erated, which drives the RESET pin low to reset the inter-
nal hardware.
The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.
T
W DTR
Interval of BIT
×
=
2
3
n
Source clock
Binary-counter
WDTR
WDTIF interrupt
WDTR
← "0100_0011
B"
1
0
Match
Detect
Counter
Clear
1
2
30
BIT overflow
3
WDT reset
reset


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