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GMS81C2112 Datasheet(PDF) 53 Page - Hynix Semiconductor |
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GMS81C2112 Datasheet(HTML) 53 Page - Hynix Semiconductor |
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53 / 107 page  GMS81C2112/GMS81C2120 JUNE. 2001 Ver 1.00 47 8-bit Event Counter Mode In this mode, counting up is started by an external trigger. This trigger means falling edge or rising edge of the EC0 pin input. Source clock is used as an internal clock selected with timer mode register TM0. The contents of timer data register TDR0 is compared with the contents of the up- counter T0. If a match is found, an timer interrupt request flag T0IF is generated, and the counter is cleared to “0”. The counter is restart and count up continuously by every falling edge or rising edge of the EC0 pin input. The maximum frequency applied to the EC0 pin is fXIN/2 [Hz]. In order to use event counter function, the bit 2 of the R5 function register (R5FUNC.2) is required to be set to “1”. After reset, the value of timer data register TDR0 is unde- fined, it should be initialized to between 1H~FFHnot to "0"The interval period of Timer is calculated as below equation. Figure 12-5 Event Counter Mode Timing Chart Figure 12-6 Count Operation of Timer / Event counter Period (sec) 1 f XIN ----------- 2 Divide Ratio TDR0 × × × = 0 1 2 1 0 n 2 n-1 n ECn pin input Up-counter TDR1 T1IF interrupt Start count Timer 1 (T1IF) Interrupt TDR1 TIME Occur interrupt Occur interrupt stop clear & start disable enable Start & Stop T1ST T1CN Control count T1ST = 0 T1ST = 1 T1CN = 0 T1CN = 1 |
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