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GMS81C2112 Datasheet(PDF) 67 Page - Hynix Semiconductor

No. de Pieza. GMS81C2112
Descripción  HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
Descarga  107 Pages
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Fabricante  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/ko/index.jsp
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GMS81C2112 Datasheet(HTML) 67 Page - Hynix Semiconductor

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GMS81C2112/GMS81C2120
JUNE. 2001 Ver 1.00
61
14.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of
SIOM) to “1”. After one cycle of SCK, SIOST is cleared
automatically to “0”. The serial output data from 8-bit shift
register is output at falling edge of SCLK. And input data
is latched at rising edge of SCLK pin. When transmission
clock is counted 8 times, serial I/O counter is cleared as
‘0”. Transmission clock is halted in “H” state and serial I/
O interrupt(IFSIO) occurred.
Figure 14-3 SPI Timing Diagram at POL=0
Figure 14-4 SPI Timing Diagram at POL=1
D1
D2
D3
D4
D6
D7
D0
D5
D1
D2
D3
D4
D6
D7
D0
D5
SIOST
SCLK [R53]
(POL=0)
SOUT [R55]
SIN [R54]
SPIIF
(SPI Int. Req)
(IOSW=0)
D1
D2
D3
D4
D6
D7
D0
D5
IOSWIN [R55]
(IOSW=1)
SIOSF
(SPI Status)
D1
D2
D3
D4
D6
D7
D0
D5
D1
D2
D3
D4
D6
D7
D0
D5
SIOST
SCLK [R53]
(POL=1)
SOUT [R55]
SIN [R54]
SPIIF
(SPI Int. Req)
(IOSW=0)
D1
D2
D3
D4
D6
D7
D0
D5
IOSWIN [R55]
(IOSW=1)
SIOSF
(SPI Status)


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