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GMS81C2112 Datasheet(PDF) 71 Page - Hynix Semiconductor |
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GMS81C2112 Datasheet(HTML) 71 Page - Hynix Semiconductor |
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71 / 107 page 
GMS81C2112/GMS81C2120 JUNE. 2001 Ver 1.00 65 16. INTERRUPTS The GMS81C21xx interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). Nine interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 16-2. The External Interrupts INT0 and INT1 each can be transi- tion-activated (1-to-0 or 0-to-1 transition) by selection IEDS. The flags that actually generate these interrupts are bit INT0F and INT1F in register IRQH. When an external in- terrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 ~ Timer 1 Interrupts are generated by TxIF which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The Watchdog timer Interrupt is generated by WDTIF which set by a match in Watchdog timer register. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer counter register. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on page 21), the interrupt enable register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. Below table shows the Interrupt priority. Vector addresses are shown in Figure 8-6 on page 23. In- terrupt enable registers are shown in Figure 16-3. These registers are composed of interrupt enable flags of each in- terrupt source and these flags determines whether an inter- rupt will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which dis- ables all interrupts at once. Figure 16-1 Interrupt Request Flag Reset/Interrupt Symbol Priority Hardware Reset External Interrupt 0 External Interrupt 1 Timer/Counter 0 Timer/Counter 1 - - - - ADC Interrupt Watchdog Timer Basic Interval Timer Serial Communication RESET INT0 INT1 TIMER0 TIMER1 - - - - ADC WDT BIT SCI - 1 2 3 4 - - - - 5 6 7 8 R/W INT0IF INITIAL VALUE: 0000 ----B ADDRESS: 0E4H IRQH INT1IF MSB T0IF T1IF R/W Timer/Counter 1 interrupt request flag SPIF R/W ADIF Serial Communication interrupt request flag INITIAL VALUE: 0000 ----B ADDRESS: 0E5H IRQL WDTIF MSB LSB - - - BITIF R/W Timer/Counter 0 interrupt request flag - R/W R/W R/W R/W - - -- Basic Interval imer interrupt request flag Watchdog timer interrupt request flag A/D Conver interrupt request flag External interrupt 1 request flag External interrupt 0 request flag LSB - - -- - - -- |
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