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GMS81C2112 Datasheet(PDF) 72 Page - Hynix Semiconductor

No. de Pieza. GMS81C2112
Descripción  HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
Descarga  107 Pages
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Fabricante  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/ko/index.jsp
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GMS81C2112 Datasheet(HTML) 72 Page - Hynix Semiconductor

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GMS81C2112/GMS81C2120
66
JUNE. 2001 Ver 1.00
.
Figure 16-2 Block Diagram of Interrupt
Figure 16-3 Interrupt Enable Flag
Timer 0
INT1
INT0
INT0IF
IENH
Interrupt Enable
Interrupt Enable
IRQH
IRQL
Interrupt
Vector
Address
Generator
Internal bus line
Register (Lower byte)
Internal bus line
Register (Higher byte)
Release STOP
To CPU
Interrupt Master
Enable Flag
I-flag
IENL
I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.
[0E2H]
[0E3H]
[0E4H]
[0E5H]
INT1IF
T0IF
Timer 1
T1IF
A/D Converter
ADIF
SIOIF
BITIF
Watchdog Timer
Serial
BIT
WDTIF
Communication
T1E
R/W
INT0E
INITIAL VALUE: 0000 ----B
ADDRESS: 0E2H
IENH
INT1E
MSB
T0E
R/W
Timer/Counter 1 interrupt enable flag
SPIE
R/W
ADE
Serial Communication interrupt enable flag
INITIAL VALUE: 0000 ----B
ADDRESS: 0E3H
IENL
WDTE
MSB
LSB
-
-
-
BITE
R/W
Timer/Counter 0 interrupt enable flag
-
R/W
R/W
R/W
R/W
-
-
--
Basic Interval imer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Convert interrupt enable flag
External interrupt 1 enable flag
External interrupt 0 enable flag
0: Disable
1: Enable
VALUE
LSB
-
-
--
-
-
--


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