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GMS81C5108 Datasheet(PDF) 84 Page - Hynix Semiconductor |
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GMS81C5108 Datasheet(HTML) 84 Page - Hynix Semiconductor |
84 / 102 page GMS81C5108 JUNE 2001 Ver 1.0 81 22. RESET The GMS81C5108 have two types of reset generation pro- cedures; one is an external reset input, the other is a watch- dog timer reset. Table 22-1 shows on-chip hardware ini- tialization by reset action. Table 22-1 Initializing Internal Status by Reset Action 22.1 External Reset Input The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin to low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is ap- plied, and the internal state is initialized. After reset, 65.5ms (at 4MHz) add with 7 oscillator periods are re- quired to start execution as shown in Figure 22-2. Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it. When the RESET pin input goes to high, the reset opera- tion is released and the program execution starts at the vec- tor address stored at FFFEH - FFFFH. A connection for simple power-on-reset is shown in Figure 22-1. Figure 22-1 Simple Power-on-Reset Circuit Figure 22-2 Timing Diagram after RESET 22.2 Watchdog Timer Reset Refer to “13.2 Watch Dog Timer” on page 57. On-chip Hardware Initial Value On-chip Hardware Initial Value Program counter (PC) (FFFFH) - (FFFEH) Peripheral clock On RAM page register (RPR) 0 SVD Enable G-flag (G) 0 Control registers Refer to Table 8-1 on page 25 Operation mode Main-frequency clock Voltage Booster Disable RESET + − VDD VDD GND Mask Option MCU 100k Ω 1uF MAIN PROGRAM System Clock ? ? FFFE FFFF Stabilization Time tST = 65.5mS at 4MHz RESET ADDRESS DATA 1 2 3 4 5 6 7 ?? Start ? ? ? FE ? ADL ADH OP BUS BUS RESET Process Step tST = x 256 fMAIN ÷1024 1 |
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