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GMS81C7008 Datasheet(PDF) 71 Page - Hynix Semiconductor |
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GMS81C7008 Datasheet(HTML) 71 Page - Hynix Semiconductor |
71 / 123 page GMS81C7008/7016 APR., 2001 Ver 2.01 67 Example: Register save using push and pop instructions General-purpose register save/restore using push and pop instruc- tions; 17.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK inter- rupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 17-5. Figure 17-5 Execution of BRK/TCALL0 17.3 Multi Interrupt If two requests of different priority levels are received simulta- neously, the request of higher priority level is serviced. If re- qu est s of th e int errup t are received at t he same t ime simultaneously, an internal polling sequence determines by hard- ware which request is serviced. However, multiple processing through software for special fea- tures is possible. Generally when an interrupt is accepted, the I- flag is cleared to disable any further interrupt. But as user sets I- flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH A PUSH X PUSH Y LDM IENH,#08H ; Enable INT0 only LDM IENL,#00H ; Disable other EI ; Enable Interrupt : : : : LDM IENH,#0FFH ; Enable all interrupts LDM IENL,#0FFH POP Y POP X POP A RETI . Figure 17-6 Execution of Multi Interrupt INTxx: PUSH A PUSH X PUSH Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. interrupt processing POP Y POP X POP A RETI ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return B-FLAG BRK INTERRUPT ROUTINE RETI TCALL0 ROUTINE RET BRK or TCALL0 =0 =1 enable INT0 TIMER 1 service INT0 service Main Program service Occur TIMER1 interrupt Occur INT0 EI disable other enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable “EI” in the TIMER1 routine. |
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