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ICS9169C-271 Datasheet(PDF) 2 Page - Integrated Circuit Systems

No. de Pieza. ICS9169C-271
Descripción  Frequency Generator for Pentium™ Based Systems
Descarga  8 Pages
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Fabricante  ICST [Integrated Circuit Systems]
Página de inicio  http://www.icst.com
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ICS9169C-271 Datasheet(HTML) 2 Page - Integrated Circuit Systems

   
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ICS9169C-271
Pin Descriptions
* The internal pull up will vary from 350K to 500K based on temperature
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD
PWR
Power for device logic and crystal oscillator circuit and
14.318 MHz output.
2X1
IN
XTAL or external reference frequency input. This input
includes XTAL load capacitance and feedback bias for a
12-16MHz crystal, nominally 14.31818MHz External crystal
load of 30pF to GND recommended for VDD power on faster
than 2.0ms.
3
X2
OUT
XTAL output which includes XTAL load capacitance.
External crystal load of 10pF to GND recommended for VDD
power on faster than 2.0ms.
4,11,20,26
GND
PWR
Ground for device logic.
5
CPU(1)
OUT
Processor clock output which is a multiple of the input
reference frequency.
FS0
IN
Frequency multiplier select pins. 350K internal pull up.
6,7,9,10,15,16,17,18,19
CPU
(2:5) (8:12)
OUT
Processor clock outputs which are a multiple of the input
reference frequency.
8
VDDC1
PWR
Power for CPU(1:6) output buffers only. Can be reduced VDD
for 2.5V (2.375-2.62V) next generation processor clocks.
12
CPU(6)
OUT
Processor clock output which is a multiple of the input
reference frequency internal pull up devices.
FS1
IN
Frequency multiplier select pin. See shared pin description.
350K internal pull up.
13
CPU(7)
OUT
Processor clock output which is a multiple of the input
reference frequency internal pull up devices.
FS2
IN
Frequency multiplier select pin. See shared pin description.
350K internal pull up.
14
VDDC2
PWR
Power for CPU PLL, logic and CPU(7:12)output buffers. Must
be nominal 3.3V (3.0 to 3.7V)
21,22,24,25,27,28
BUS (1:6)
OUT
BUS clock outputs which are a multiple of the input
reference clock.
23
VDDB
PWR
Power for BUS clock buffers BUS(1:6).
29
VDDF
PWR
Power for fixed clock buffer (48 MHz, 24 Mhz).
30
24MHz
OUT
Fixed 24MHz clock (assuming a 14.31818MHz REF
frequency).
31
48MHz
OUT
Fixed 48MHz clock (assuming a 14.31818MHz
REF frequency).
32
REF
OUT
Fixed 14.31818MHz clock (assuming a 14.31818MHz
REF frequency).
BSEL
IN
Selection for synchronous or asynchronous bus clock
operation. See shared pin programming description late in this
data sheet for further explanation. 350K internal pull up.


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