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ICS9169C-271 Datasheet(PDF) 1 Page - Integrated Circuit Systems

No. de pieza ICS9169C-271
Descripción Electrónicos  Frequency Generator for Pentium™ Based Systems
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Fabricante Electrónico  ICST [Integrated Circuit Systems]
Página de inicio  http://www.icst.com
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ICS9169C-271 Datasheet(HTML) 1 Page - Integrated Circuit Systems

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Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9169C-271
Block Diagram
Frequency Generator for Pentium™ Based Systems
9169C-271RevC060297P
Pin Configuration
The ICS9169C-271 is a low-cost frequency generator
designed specifically for Pentium based chip set systems.
The integrated buffer minimizes skew and provides all the
clocks required. A 14.318 MHz XTAL oscillator provides
the reference clock to generate standard Pentium frequencies.
The CPU clock makes gradual frequency transitions without
violating the PLL timing of internal microprocessor clock
multipliers. A raised frequency setting of 68.5MHz is available
for Turbo-mode of the 66.8MHz CPU. The ICS9169C-271
contains 12 CPU clocks, 4 PCI clocks, 1 REF at 48MHz and 1 at
24MHz.
The twelve CPU clock outputs provide sufficient clocks for
the CPU, chip set, memory and up to two DIMM connectors
(with four clocks to each DIMM). Either synchronous(CPU/
2) or asynchronous (32 MHz) PCI busoperation can be selected
by latching data on the BSEL input.
32-Pin SOIC/SOJ
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
Pentium is a trademark of Intel Corporation.
Twelve selectable CPU clocks operate up to 83.3MHz
Maximum CPU jitter of ± 200ps
Six BUS clocks support sync or async bus operation
±250ps skew for all synchronous clock edges
CPU clocks BUS clocks skew 1-4ns (CPU early)
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range, CPU(1:12) outputs
2.5V(2.375-2.62V) VDD option
32-pin SOIC/SOJ package
Logic inputs latched at Power-On for frequency
selection saving pins as Input/Output
48 MHz clock for USB support and 24 MHz clock
for FD.
ADDRES S
S ELECT
C P U (1:12)
(M H z)
B U S (1:6)M H z
48M H z
24M H z
R E F
FS2 FS1
FS0
BSEL=1
BSEL=0
00
0
50
25
32
48
24
REF
00
1
60
30
32
48
24
REF
0
1
0
66.8
33.4
32
48
24
REF
0
1
1
75.9
32
32
48
24
REF
1
0
0
55
27.5
32
48
24
REF
1
0
1
75.9
37.5
32
48
24
REF
1
1
0
83.3
41.7
32
48
24
REF
1
1
1
68.5
34.25
32
48
24
REF
VDD Groups:
VDD = X1, X2, REF/BSEL
VDDC1 = CPU1-6
VDDC2 = CPU7-12 & PLL Core
VDDB = BUS1-6
VDDF = 48/24 MHz
Latched Inputs:
L1 = BSEL
L2 = FS0
L3 = FS1
L4 = FS2
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.


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