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IDT29FCT52A Datasheet(PDF) 2 Page - Integrated Device Technology

No. de Pieza. IDT29FCT52A
Descripción  FAST CMOS OCTAL REGISTERED TRANSCEIVERS
Descarga  7 Pages
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Fabricante  IDT [Integrated Device Technology]
Página de inicio  http://www.idt.com
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IDT29FCT52A Datasheet(HTML) 2 Page - Integrated Device Technology

   
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IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Name
I/O
Description
A0-7
I/O
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
B0-7
I/O
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
CPA
I
Clock for the A Register. When
CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal.
CEA
I
Clock Enable for the A Register. When
CEA is LOW, data is entered into the A Register on the LOW-to-HIGH
transition of the CPA signal. When
CEA is HIGH, the A Register holds its contents, regardless of CPA signal
transitions.
OEB
I
Output Enable for the A Register. When
OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When
OEB is HIGH, the B0-7 outputs are in the high-impedance state.
CPB
I
Clock for the B Register. When
CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal.
CEB
I
Clock Enable for the B Register. When
CEB is LOW, data is entered into the B Register on the LOW-to-HIGH
transition of the CPB signal. When
CEB is HIGH, the B Register holds its contents, regardless of CPB signal
transitions.
OEA
I
Output Enable for the B Register. When
OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When
OEA is HIGH, the A0-7 outputs are in the high-impedance state.
2533 tbl 01
PIN CONFIGURATIONS
DIP/CERPACK/SOIC
TOP VIEW
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
Vcc
16
15
14
13
P24-1,
D24-1,
E24-1
&
SO24-2
A6
A5
A4
A3
A2
CEB
CEA
CPB
CPA
OEA
A1
A0
A7
B6
B5
B4
B3
B2
B1
B
B7
0
OEB
REGISTER FUNCTION TABLE
(1)
(Applies to A or B Register)
Inputs
Internal
DCP
CE
CE
Q
Function
X
X
H
NC
Hold Data
L
L
L
Load Data
H
LH
2533 tbl 02
OUTPUT CONTROL
(1)
Internal
Y-Outputs
OE
OE
Q
52
53
Function
H
X
Z
Z
Disable Outputs
L
L
L
H
Enable Outputs
LH
HL
NOTE:
2533 tbl 03
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition
5
6
7
8
9
10
11
L28-1
25
24
23
22
21
20
19
INDEX
B4
B3
B2
B1
B0
OEB
NC
NC
A5
A4
A3
A2
A1
A0
12 13 14 15 16 17 18
43
2
1
28 27 26
LCC
TOP VIEW
2533 drw 02


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