Pin

Number

Pin

Name

Description

1

PBRST

Pushbutton reset input. This input is debounced and can be driven with external logic

signals or a mechanical pushbutton to actively force a reset. All pulses less than 1ms in

duration on the PBRST pin are ignored. Any pulse with a duration of 20ms or greater is

guaranteed to cause a reset. PBRST has an internal 40k

Ω (typical) pull-up resistor to V

2

TD

Time delay input. This input selects the timebase used by the watchdog timer. When TD =

0V, the watchdog timeout period is set to a nominal value of 150ms, when TD = open, the

watchdog timeout period is 1.2 sec nominally.

3

TOL

tolerance level is selected.

4

GND

Ground pin, 0V reference.

5

RST

PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout

goes high.

6

RST

PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout

goes high. Open-drain output.

7

ST

Input to the watchdog timer. If ST does not see a transition from high to low within the

watchdog timeout period, RST and RST will be asserted.

8

Power supply input.

8

1

Reset

Generator

6

4

-

+

ST

RST

GND

3

7

2

Trip Point

Select

Ref

Manual Reset

Debounce

Watchdog

Timer

Timeout

Select

5

RST

TOL

PBRST

TD

µP Supervisory Circuit

Preliminary

Pin Functions

Block Diagram

Impala Linear Corporation

3

(408) 574-3939

www.impalalinear.com

October 1999

ILC1832 1.1