 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD5317 Datasheet(PDF) 5 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD5317 Datasheet(HTML) 5 Page - Analog Devices |
|
|
5 / 28 page  AD5307/AD5317/AD5327 Rev. C | Page 5 of 28 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 2. A, B Versions1 Parameter2, 3 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time VREF = VDD = 5 V AD5307 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0) AD5317 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300) AD5327 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry Digital Feedthrough 0.5 nV-s SDO Feedthrough 4 nV-s Daisy-chain mode; SDO load is 10 pF Digital Crosstalk 0.5 nV-s Analog Crosstalk 1 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p; unbuffered mode Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz 1 Temperature range (A, B versions): −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization; not production tested. 3 See the Terminology section. TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. A, B Versions Parameter1, , 2 3 Limit at TMIN, TMAX Unit Conditions/Comments t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC to SCLK falling edge set-up time t5 5 ns min Data set-up time t6 4.5 ns min Data hold time t7 5 ns min SCLK falling edge to SYNC rising edge t8 50 ns min Minimum SYNC high time t9 20 ns min LDAC pulse width t10 20 ns min SCLK falling edge to LDAC rising edge t11 20 ns min CLR pulse width t12 0 ns min SCLK falling edge to LDAC falling edge t134, 5 20 ns max SCLK rising edge to SDO valid (VDD = 3.6 V to 5.5 V) 25 ns max SCLK rising edge to SDO valid (VDD = 2.5 V to 3.5 V) t14 5 ns min SCLK falling edge to SYNC rising edge t15 8 ns min SYNC rising edge to SCLK rising edge t16 0 ns min SYNC rising edge to LDAC falling edge 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 3 and Figure 4. 4 This is measured with the load circuit of Figure 2. t13 determines maximum SCLK frequency in daisy-chain mode. 5 Daisy-chain mode only. |
Número de pieza similar - AD5317_15 |
|
Descripción similar - AD5317_15 |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
