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AD5541 Datasheet(PDF) 4 Page - Analog Devices

No. de Pieza. AD5541
Descripción  2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs
Descarga  20 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD5541 Datasheet(HTML) 4 Page - Analog Devices

 
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AD5541/AD5542
Data Sheet
Rev. F | Page 4 of 20
Parameter1
Min
Typ
Max
Unit
Test Conditions
POWER REQUIREMENTS
Digital inputs at rails
VDD
2.7
5.5
V
IDD
125
150
μA
Power Dissipation
0.625
0.825
mW
1 Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C.
2 Reference input resistance is code-dependent, minimum at 0x8555.
3 Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V ±10%, VREF= 2.5 V, VINH = 3 V and 90% of VDD, VINL = 0 V and 10% of VDD, AGND = DGND = 0 V; −40°C < TA <
+85°C, unless otherwise noted.
Table 3.
Parameter1, 2
Limit
Unit
Description
f
SCLK
25
MHz max
SCLK cycle frequency
t
1
40
ns min
SCLK cycle time
t
2
20
ns min
SCLK high time
t
3
20
ns min
SCLK low time
t
4
10
ns min
CS low to SCLK high setup
t
5
15
ns min
CS high to SCLK high setup
t
6
30
ns min
SCLK high to CS low hold time
t
7
20
ns min
SCLK high to CS high hold time
t
8
15
ns min
Data setup time
t
9
4
ns min
Data hold time (V
INH = 90% of VDD, VINL = 10% of VDD)
t
9
7.5
ns min
Data hold time (V
INH = 3V, VINL = 0 V)
t
10
30
ns min
LDAC pulse width
t
11
30
ns min
CS high to LDAC low setup
t
12
30
ns min
CS high time between active periods
1 Guaranteed by design and characterization. Not production tested
2 All input signals are specified with t
R = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
SCLK
CS
DIN
DB15
LDAC*
t6
t4
t12
t8
t5
t2
t3
t1
t7
t5
t11
t10
*AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED.
Figure 3. Timing Diagram


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