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AD6636 Datasheet(PDF) 73 Page - Analog Devices |
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AD6636 Datasheet(HTML) 73 Page - Analog Devices |
73 / 80 page AD6636 Rev. A | Page 73 of 80 <1:0>: Number of AGC Average Samples. This defines the number of samples to be averaged before they are sent to the CIC decimating filter (see Table 43). Table 43. Number of AGC Average Samples AGC Average Samples <1:0> Number of Samples Taken 00 1 01 2 10 3 11 4 AGC Pole Location <7:0> This 8-bit register is used to define the open-loop filter pole location P. Its value can be set from 0 to 0.996 in steps of 0.0039. This value of P is updated in the AGC loop each time the AGC is initialized. This open-loop pole location directly impacts the closed-loop pole locations, see the Automatic Gain Control section. AGC Desired Level <7:0> This register contains the desired signal level or desired clipping level, depending on operational mode. This desired request level (R) can be set in dB from 0 to 23.99 in steps of 0.094 dB. The request level (R) in dB should be converted to a register setting by Register Value = round ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ×64 ) 2 ( log 20 10 R AGC Loop Gain2 <7:0> This 8-bit register is used to define the second possible open- loop gain, K2. Its value can be set from 0 to 0.996 in steps of 0.0039. This value of K2 is updated each time the AGC is initialized. When the magnitude-of-error signal in the loop is greater than the AGC error threshold, then K2 is used by the loop. K2 is updated only when the AGC is initialized. AGC Loop Gain1 <7:0> This 8-bit register is used to define the open-loop gain K1. Its value can be set from 0 to 0.996 in steps of 0.0039. This value of K is updated in the AGC loop each time the AGC is initialized. When the magnitude-of-error signal in the loop is less than the AGC error threshold, then K1 is used by the loop. K1 is updated only when the AGC is initialized. I Path Signature Register <15:0> This 16-bit signature register is for the I path of the channel logic. The signature register records data on the networks that leave the channel logic just before entering the second data router. Q Path Signature Register <15:0> This 16-bit signature register is for the Q path of the channel logic. The signature register records data on the networks that leave the channel logic just before entering the second data router. BIST Control <15:0> <15>: Disable Signature Generation Bit. When this bit is active high, the signature registers do not produce a pseudorandom output value, but instead directly load the 24-bit input data. When this bit is cleared, the signature register produces a pseudorandom output for every clock cycle that it is active. See the User-Configurable, Built-In Self-Test (BIST) section for details. <14:0>: BIST Timer Bits. The <14:0> bits of this register form a 15-bit word that is loaded into the BIST timer. After loading the BIST timer, the signature register is enabled for operation while the timer is actively counting down. (See the User- Configurable, Built-In Self-Test (BIST) section.) OUTPUT PORT REGISTER MAP This part of the memory map deals with the output data and controls for parallel output ports. Parallel Port Output Control <23:0> <23>: Port C Append RSSI Bit. When this bit is set, an RSSI word is appended to every I/Q output sample, irrespective of whether the RSSI word is updated in the AGC. When this bit is cleared, an RSSI word is appended to an I/Q output sample only when the RSSI word is updated. The RSSI word is not output for subsequent I/Q samples until the next time the RSSI is updated in the AGC. <22>: Port C, Data Format Bit. When this bit is set, the port is configured for 8-bit parallel I/Q mode. When cleared, the port is configured for 16-bit interleaved I/Q mode. See the Parallel Port Output section for details. <21>: Port C, AGC5 Enable Bit. When this bit is set, AGC5 data (I/Q data) is output on parallel Output Port C (data bus). When this bit is cleared, AGC5 data does not appear on Output Port C. <20>: Port C, AGC4 Enable Bit. Similar to Bit <21> for AGC4. <19>: Port C, AGC3 Enable Bit. Similar to Bit <21> for AGC3. <18>: Port C, AGC2 Enable Bit. Similar to Bit <21> for AGC2. <17>: Port C, AGC1 Enable Bit. Similar to Bit <21> for AGC1. <16>: Port C, AGC0 Enable Bit. Similar to Bit <21> for AGC0. |
Número de pieza similar - AD6636_15 |
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Descripción similar - AD6636_15 |
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