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ACS132MS Datasheet(PDF) 1 Page - Intersil Corporation

No. de Pieza. ACS132MS
Descripción  Radiation Hardened Quad 2-Input NAND Schmitt Trigger
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Fabricante  INTERSIL [Intersil Corporation]
Página de inicio  http://www.intersil.com/cda/home
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ACS132MS Datasheet(HTML) 1 Page - Intersil Corporation

   
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ACS132MS
Radiation Hardened Quad 2-Input NAND
Schmitt Trigger
The Radiation Hardened ACS132MS is a Quad 3-Input NAND
Gate with Schmitt Trigger inputs. When any input to one of the
gates is at a LOW level, the corresponding Y output will be
HIGH. A HIGH level on both inputs will cause the output for that
gate to be LOW. The Schmitt Trigger input stage provides
400mV (Min) of hysteresis and permits input signals with longer
rise times. All inputs are buffered and the outputs are designed
for balanced propagation delay and transition times.
The ACS132MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS132MS are
contained in SMD 5962-98625. A “hot-link” is provided
on our homepage with instructions for downloading.
http://www.intersil.com/data/sm/index.htm
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under any Conditions
- Total Dose . . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD (Si)
- SEU Immunity . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels . . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)
• Hysteresis Voltage . . . . . . . . . . . . . . . . . . . . 400mV (Min)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . .
±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100
µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 12ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
ORDERING NUMBER
INTERNAL MKT. NUMBER
TEMP. RANGE (oC)
PACKAGE
DESIGNATOR
5962F9862501VCC
ACS132DMSR-03
-55 to 125
14 Ld SBDIP
CDIP2-T14
ACS132D/SAMPLE-03
ACS132D/SAMPLE-03
25
14 Ld SBDIP
CDIP2-T14
5962F9862501VXC
ACS132KMSR-03
-55 to 125
14 Ld Flatpack
CDFP4-F14
ACS132K/SAMPLE-03
ACS132K/SAMPLE-03
25
14 Ld Flatpack
CDFP4-F14
5962F9862501V9A
ACS132HMSR-03
25
Die
N/A
Pinouts
ACS132MS
(SBDIP)
TOP VIEW
ACS132MS
(FLATPACK)
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
VCC
B4
A4
Y4
B3
A3
Y3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
A1
B1
Y1
A2
B2
Y2
GND
VCC
B4
A4
Y4
B3
A3
Y3
Data Sheet
November 1998
File Number
4546


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