10-11

Detailed Description

The AD7523 and AD7533 are monolithic multiplying D/A

converters. A highly stable thin film R-2R resistor ladder

network and NMOS SPDT switches form the basis of the

converter circuit, CMOS level shifters permit low power

TTL/CMOS compatible operation. An external voltage or

current reference and an operational amplifier are all that is

required for most voltage output applications.

A simplified equivalent circuit of the DAC is shown in the

Functional Diagram. The NMOS SPDT switches steer the

must be held at ground potential. This configuration main-

tains a constant current in each ladder leg independent of

the input code.

Converter errors are further reduced by using separate

metal interconnections between the major bits and the out-

puts. Use of high threshold switches reduce offset (leakage)

errors to a negligible level.

The level shifter circuits are comprised of three inverters with

positive feedback from the output of the second to the first,

see Figure 1. This configuration results in TTL/CMOS

compatible operation over the full military temperature

range. With the ladder SPDT switches driven by the level

shifter, each switch is binarily weighted for an ON resistance

proportional to the respective ladder leg current. This

assures a constant voltage drop across each switch,

creating equipotential terminations for the 2R ladder

resistors and high accurate leg currents.

Typical Applications

Unipolar Binary Operation - AD7523 (8-Bit DAC)

The circuit configuration for operating the AD7523 in

unipolar mode is shown in Figure 2. With positive and

multiplication. The “Digital Input Code/Analog Output Value”

table for unipolar mode is given in Table 1.

NOTES:

1. R1 and R2 used only if gain adjustment is required.

2. CF1 protects AD7523 and AD7533 against negative transients.

FIGURE 2. UNIPOLAR BINARY OPERATION

Zero Offset Adjustment

1. Connect all digital inputs to GND.

2. Adjust the offset zero adjust trimpot of the output

operational amplifier for 0V

Gain Adjustment

1. Connect all digital inputs to V+.

2

250

250

terminal.

V+

TTL/

CMOS INPUT

13

4

5

6

7

2

89

TO LADDER

FIGURE 1. CMOS SWITCH

TABLE 1. UNlPOLAR BINARY CODE - AD7523

DIGITAL INPUT

MSB

LSB

ANALOG OUTPUT

11111111

10000001

10000000

01111111

00000001

00000000

NOTE:

1.

.

15

16

1

4

11

3

2

AD7523/

MSB

LSB

14

+15V

GND

OUT1

OUT2

6

-

+

DATA

INPUTS

AD7533

±10V

R2

CR1

V

REF

255

256

----------





–

V

REF

129

256

----------





–

V

REF

128

256

----------





–

V

REF

2

-----------------

–

=

V

REF

127

256

----------





–

V

REF

1

256

----------





–

V

REF

0

256

----------





–

0

=

1 LSB

2

8

–

() V

REF

()

1

256

----------



 V

REF

()

==

AD7523, AD7533