AD9480_15 datasheet(8/28 Pages) AD

No. de pieza	AD9480

Descripción Electrónicos	8-Bit, 250 MSPS 3.3 V A/D Converter

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Fabricante Electrónico	AD [Analog Devices]

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AD9480

Rev. A | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

CLK–

AVDD

AGND

D0_C (LSB)

DRGND

DRVDD

CLK+

D0_T (LSB)

D1_C

D1_T

D2_C

33

32

31

30

29

28

27

26

25

24

23

AGND

AVDD

AGND

DRGND

S1

PDWN

SENSE

D7_T (MSB)

D7_C (MSB)

D6_T

D6_C

13 14

15

16 17 18

19

20

21

22

PIN 1

NC = NO CONNECT

44 43 42

41

40 39 38

37

36

35

34

AD9480

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

No.

Mnemonic

Description

No.

Mnemonic

Description

1

CLK+

Input Clock—True

23

D6_C

Data Output Bit 6—Complement

2

CLK−

Input Clock—Complement

24

D6_T

Data Output Bit 6—True

3

AVDD

3.3 V Analog Supply

25

D7_C

Data Output Bit 7—Complement (MSB)

4

AGND

Analog Ground

26

D7_T

Data Output Bit 7—True (MSB)

5

DRVDD

3.3 V Digital Output Supply

27

DRGND

Digital Ground

6

DRGND

Digital Ground

28

S1

Data Format Select and Duty-Cycle Stabilizer Selection

(See Table 8)

7

D0_C

Data Output Bit 0—Complement (LSB)

29

PDWN

Power-Down Selection (AVDD = Power Down)

8

D0_T

Data Output Bit 0—True (LSB)

30

AGND

Analog Ground

9

D1_C

Data Output Bit 1—Complement

31

AVDD

3.3 V Analog Supply

10

D1_T

Data Output Bit 1—True

32

AGND

Analog Ground

11

D2_C

Data Output Bit 2—Complement

33

SENSE

Reference Mode Selection (See Table 9)

12

D2_T

Data Output Bit 2—True

34

VREF

Voltage Reference Input/Output

13

D3_C

Data Output Bit 3—Complement

35

AGND

Analog Ground

14

D3_T

Data Output Bit 3—True

36

AVDD

3.3 V Analog Supply

15

DRGND

Digital Ground

37

AGND

Analog Ground

16

DCO−

Data Clock Output—Complement

38

VIN−

Analog Input—Complement

17

DCO+

Data Clock Output—True

39

VIN+

Analog Input—True

18

DRVDD

3.3 V Digital Output Supply

40

AGND

Analog Ground

19

D4_C

Data Output Bit 4—Complement

41

AVDD

3.3 V Analog Supply

20

D4_T

Data Output Bit 4—True

42

LVDSBIAS

LVDS Output Current Adjust

21

D5_C

Data Output Bit 5—Complement

43

NC1

No Connect (Leave Floating)

22

D5_T

Data Output Bit 5—True

44

AGND

Analog Ground

1 Pin 43 will self-bias to 1.5 V. It can be left floating (as recommended) or tied to AVDD or ground with no ill effects.

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