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AD9661A Datasheet(PDF) 2 Page - Analog Devices |
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AD9661A Datasheet(HTML) 2 Page - Analog Devices |
2 / 12 page AD9661A–SPECIFICATIONS Test AD9661AKR Parameter Level Temp Min Typ Max Units Conditions ANALOG INPUT Input Voltage Range, POWER LEVEL IV Full VREF VREF + 1.6 V Input Bias Current, POWER LEVEL I +25 °C –50 +50 µA Analog Bandwidth, Control Loop 1 V +25 °C 25 MHz CHOLD = 33 pF, RF = 1 kΩ, CF = 2 pF Input Voltage Range, LEVEL SHIFT IN IV Full 0.1 1.6 V Input Bias Current, LEVEL SHIFT IN I +25 °C –10 0 µA Analog Bandwidth, Level Shift 2 V Full 130 MHz Level Shift Offset I +25 °C –32 +32 mV Level Shift Gain I +25 °C 0.95 1.0 1.05 V/V OUTPUTS Output Current, IOUT I +25 °C 120 mA VOUT = 2.5 V Output Compliance Range IV +25 °C 2.50 5.25 V Idle Current I +25 °C 2 5.0 mA PULSE = LOW, DISABLE = LOW Disable Current IV +25 °C 1.0 µA PULSE = LOW, DISABLE = HIGH SWITCHING PERFORMANCE Maximum Pulse Rate V +25 °C 200 MHz Output Current –3 dB Output Propagation Delay (tPD), Rising 3 IV Full 2.9 3.9 5.0 ns Output Propagation Delay (tPD), Falling 3 IV Full 3.2 3.7 4.3 ns Output Current Rise Time 4 IV Full 1.5 2.0 ns Output Current Fall Time5 IV Full 1.5 2.0 ns CAL Aperture Delay 6 IV Full 13 ns Disable Time 7 IV +25 °C3 5 ns HOLD NODE Input Bias Current I +25 °C –200 200 nA VHOLD = 2.5 V Input Voltage Range IV Full VREF VREF + 1.6 V Open-Loop Application Only Minimum External Hold Cap V Full 25 pF TTL/CMOS INPUTS 8 Logic “1” Voltage I +25 °C 2.0 V Logic “1” Voltage IV Full 2.0 V Logic “0” Voltage I +25 °C 0.8 V Logic “0” Voltage IV Full 0.8 V Logic “1” Current I +25 °C –10 10 µAV HIGH = 5.0 V Logic “0” Current I +25 °C –1.5 mA VLOW = 0.8 V BANDGAP REFERENCE Output Voltage (VREF) I +25 °C 1.6 1.8 1.9 V Temperature Coefficient V +25 °C –0.1 mV/ °C Output Current V +25 °C –0.5 1.0 mA SENSE IN Current Gain I +25 °C 0.95 1 1.02 mA/mA Voltage I +25 °C 0.7 1.0 1.3 V Input Resistance V +25 °C <150 Ω POWER SUPPLY +VS Voltage I +25 °C 4.75 5.00 5.25 V +VS Current I +25 °C 60 75 95 mA DISABLE = HIGH, VHOLD = VREF, VS = 5.0 V NOTES 1Based on rise time of closed-loop pulse response. See Performance Curves. 2Based on rise time of pulse response. 3Propagation delay measured from the 50% of the rising/falling transition of WRITE PULSE to the 50% point of the rising/falling edge of the output modulation current. 4Rise time measured between the 10% and 90% points of the rising transition of the modulation current. 5Fall time measured between the 10% and 90% points of the falling transition of the modulation current. 6Aperture Delay is measured from the 50% point of the rising edge of WRITE PULSE to the time when the output modulation begins to recalibrate, WRITE CAL is held during this test. 7Disable Time is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable is similar to fall time during normal operation. 8PULSE, PULSE2, DISABLE, and CAL are TTL/CMOS compatible inputs. Specifications subject to change without notice. REV. 0 –2– (+VS = +5 V, Temperature = +25 C unless otherwise noted) |
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