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ADF4113HVBCPZ-RL7 Datasheet(PDF) 1 Page - Analog Devices

No. de pieza ADF4113HVBCPZ-RL7
Descripción Electrónicos  High Voltage Charge Pump, PLL Synthesizer
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADF4113HVBCPZ-RL7 Datasheet(HTML) 1 Page - Analog Devices

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High Voltage
Charge Pump, PLL Synthesizer
Data Sheet
ADF4113HV
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2007–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
High voltage charge pump (15 V)
2.7 V to 5.5 V power supply
200 MHz to 4.0 GHz frequency range
Pin compatible with ADF4110, ADF4111, ADF4112, ADF4113
ADF4106, and ADF4002 synthesizers
Two selectable charge pump currents
Digital lock detect
Power-down mode
Loop filter design possible with ADIsimPLL™
APPLICATIONS
Applications using high voltage VCOs
IF/RF local oscillator (LO) generation in base stations
Point-to-point radio LO generation
Clock for analog-to-digital and digital-to-analog converters
Wireless LANs, PMR
Communications test equipment
GENERAL DESCRIPTION
The ADF4113HV is an integer-N frequency synthesizer with a
high voltage charge pump (15 V). The synthesizer is designed
for use with voltage controlled oscillators (VCOs) that have
high tuning voltages (up to 15 V). Active loop filters are often
used to achieve high tuning voltages, but the ADF4113HV
charge pump can drive a high voltage VCO directly with a
passive-loop filter. The ADF4113HV can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. It consists of a
low noise digital phase frequency detector (PFD), a precision
high voltage charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
(P/P + 1).
A simple 3-wire interface controls all of the on-chip registers.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
LE
MUXOUT
ADF4113HV
CP
CE
AGND
DGND
CPGND
22
14
REFERENCE
M3 M2 M1
6
HIGH Z
N = BP + A
CHARGE
PUMP
CURRENT
SETTING
MUX
RSET
VP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
AVDD
SDOUT
24-BIT
INPUT REGISTER
DVDD
AVDD
19
13
SDOUT
REFIN
14-BIT
R COUNTER
RFINA
RFINB
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
FROM
FUNCTION
LATCH
13-BIT
B COUNTER
6-BIT
A COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
Figure 1.


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