ADF4212L_15 datasheet(5/28 Pages) AD

No. de pieza	ADF4212L

Descripción Electrónicos	Dual Low Power PLL Frequency Synthesizer

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Fabricante Electrónico	AD [Analog Devices]

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Data Sheet

ADF4212L

Rev. E | Page 5 of 28

TIMING CHARACTERISTICS

VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX, unless

otherwise noted; dBm referred to 50 Ω.

Table 3.

Parameter1

Limit at TMIN to TMAX (B Version)

Unit

Test Conditions/Comments

t1

20

ns min

LE setup time

t2

10

ns min

Data to clock setup time

t3

10

ns min

Data to clock hold time

t4

25

ns min

Clock high duration

t5

25

ns min

Clock low duration

t6

10

ns min

Clock to LE setup time

t7

20

ns min

LE pulse width

1

Guaranteed by design but not production tested.

CLK

DATA

LE

DB23 (MSB)

DB22

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t1

t2

t3

t7

t6

t4

t5

Figure 2. Timing Diagram

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