ADG406/ADG407/ADG426

Rev. B | Page 7 of 20

ADG426 TIMING DIAGRAMS

50%

50%

2V

0.8V

3V

0V

3V

A0, A1, A2, (A3)

EN

0V

WR

Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs

Figure 4 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive;

therefore, while WR is held low, the latches are transparent and

the switches respond to the address and enable inputs. This

input data is latched on the rising edge of WR.

3V

0V

0V

50%

50%

RS

SWITCH

OUTPUT

Figure 5. Reset Pulse Width and Reset Turn Off Time

Note that all digital input signals rise and fall times are