ADIS16120

Rev. B | Page 9 of 12

APPLICATIONS INFORMATION

ACHIEVING OPTIMAL NOISE PERFORMANCE

There are several system level considerations that can have an

impact on the noise and accuracy of the ADIS16120. Under-

standing and managing these factors can influence the behavior

of any high performance system.

Supply and Common Considerations

The ADIS16120 provides approximately 1.8 μF of decoupling

capacitance. This capacitance is distributed throughout the

device and should be taken into account when considering

potential noise threats on the power supply lines.

Reference Output

The same reference that is used to calibrate the offset perform-

ance of the ADIS16120 is made available for system level use.

The REFOUT pin has 1 μF of capacitance, providing a degree

of noise filtering. However, careful use of this pin is necessary,

considering that any noise or level-shifting influences introduce

errors in the output.

Bandwidth Setting

response, it should be placed close to the device. Long cable

leads and PCB traces may increase the risk of noise introduction.

USING THE ADIS16120 WITH A SUPPLY

RATIOMETRIC ADC

The RATEOUT signal of the ADIS16120 is nonratiometric; that

is, neither the null voltage nor the rate sensitivity is proportional

to the supply. Instead, they are nominally constant for dc supply

changes within the 4.75 V to 5.25 V operating range. If the

ADIS16120 is used with a supply ratiometric ADC, the 2.5 V

output of the ADIS16120 can be converted and used to make

corrections in software for the supply variations.

SECOND-LEVEL ASSEMBLY

The ADIS16120 is designed to be mounted with the header pins

either facing up (bulkhead mount) or facing down (printed circuit

board mount). In either case, the mating socket should be a Samtec

part number: CLM-112-02-L-D-A or equivalent. This family of

connectors offers multiple configurations for use in mating to the

ADIS16120. Consult the manufacturer reference material if this

connector does not match system level requirements. The recom-

mended pad/hole layout for this socket is shown in Figure 16.

Use the alignment pins identified in this figure, along with either

Figure 17 or Figure 18, to design an appropriate interface for

the ADIS16120. Note that to meet worst-case dimensional

tolerances of the entire package, the header pins extend beyond

the height of the package, requiring the mating PCB to have holes

to prevent the bottoming-out of the ADIS16120 pins. Without

the holes, a bottom-out event places the ADIS16120 under stress,

which can affect accuracy performance. Also, in either mounting

configuration, ensure that the ADIS16120 is firmly mounted to

prevent additional mechanical vibration.

0.4334 [11.0]

0.0240 [0.610]

0.019685

[0.5000]

(TYP)

0.054 [1.37]

0.0394 [1.00]

0.0394 [1.00] 0.1800

[4.57]

NON PLATED

THRU HOLE 2×

0.022±

DIA (TYP)

0.022 DIA THRU HOLE (TYP)

NON PLATED THRU HOLE

Figure 16. Mating Socket Recommended Pad Layout

Dimensions are shown in inches (millimeters)