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ADN8820 Datasheet(PDF) 7 Page - Analog Devices

No. de pieza ADN8820
Descripción Electrónicos  EDFA and CW Laser Controller
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADN8820 Datasheet(HTML) 7 Page - Analog Devices

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ADN8820
Preliminary Technical Data
Rev. PrB | Page 7 of 9
Name
Pin
Function
Connections
DITHER GENERATOR
DSEL/SD
21
4-level logic input to set dither frequency or engage
shutdown
External voltage
DCTL
36
Sets dither current as a percentage of the laser
diode current
Resistor (RDCTL) to ground
DO
35
Optional dither AC current to laser diode
To laser diode through 1 nF series capacitor
LOGIC INPUTS
MODE1
18
Sets control loop mode (see Table I)
External logic voltage
MODE0
19
Sets control loop mode (see Table I)
External logic voltage
DSEL/SD
21
Pulling voltage low engages shutdown
External voltage
SS/SB
25
Pulling voltage low engages standby
470 pF soft-start capacitor to ground; optional external
FET can pull down to engage standby
LOGIC OUTPUTS
CLGD
20
Logic high if EAOUT is within 5% to 95% of AVDD;
Logic low otherwise
POWER
PVDD
29, 34
Power for output amplifiers and digital sections
3.0 V to 5.5 V
AVDD
43
Low noise power for TIAs, limiter section, and EA
3.0 V to 5.5 V
PGND
32
Current return for output amplifiers
0 V
AGND
14
Low noise ground
0 V
VREF
13
2.5 V reference voltage
Can be used as refernce for VB, VBLP, SET, and limiter
inputs
TABLE 4. MODE CONTROL LOGIC
MODE Inputs
Error Amplifier
MUX
MODE1
MODE0
Mode Setting
-Input
+Input
Output
Description
0
0
Constant Current
EANLP
SET
LIO
Maintains a fixed current through laser diode;
generally used for calibration.
0
1
Constant Laser Power
EANLP
SET
LPO
Maintains a constant optical output power from
laser diode.
1
0
Constant Ouptut Power
EANOP
SET
OPO
Maintains a constant optical power at output of
EDFA.
1
1
Constant Gain
EANOP
IPO
OPO
Monitors both input and output optical power
to maintain constant gain from optical amplifier.
TABLE 5. PWM CLOCK FREQUENCY SELECTION LEVELS
DSEL/SD (V)
PWM Clock Frequency
Min
Max
Mode
Division
0
0.5
Shutdown
N/A
0.7
1.2
Active
fDITHER
÷2
1.3
1.8
Active
fDITHER
÷4
2.0
VDD
Active
fDITHER
÷8
Note: fDITHER is the ADN8820 dither frequency and is set by a resistor connected from RT to ground.


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