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ADP3310 Datasheet(PDF) 6 Page - Analog Devices

No. de pieza ADP3310
Descripción Electrónicos  Precision Voltage Regulator Controller
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ADP3310 Datasheet(HTML) 6 Page - Analog Devices

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ADP3310
–6–
REV. B
APPLICATION INFORMATION
The ADP3310 is very easy to use. A P-channel power MOSFET
and a small capacitor on the output is all that is needed to form
an inexpensive ultralow dropout regulator. The advantage of
using the ADP3310 controller is that it can drive a pass PMOS
FET to provide a regulated output at high current.
FET Selection
The type and size of the pass transistor are determined by the
threshold voltage, input-output voltage differential, and load
current. The selected PMOS must satisfy the physical and
thermal design requirements. Table I shows a partial list of
manufacturers providing the PMOS devices. To ensure that the
maximum VGS provided by the controller will turn on the FET
at worst case conditions (i.e., temperature and manufacturing
tolerances), the maximum available VGS must be determined.
Maximum VGS is calculated as follows:
(1) VGS = VIN – VBE – IOMAX
× RS
IOMAX = Maximum Output Current
RS = Current Sense Resistor
VBE ~ 0.7 V (Room Temp)
~ 0.5 V (Hot)
~ 0.9 V (Cold)
For Example: VIN = 5 V, VO = 3.3 V and IOMAX = 3 A,
VGS = 5 V – 0.7 V – 3 A
× 11 mΩ = 4.27 V
Equation (1) applies to a gate-to-source voltage less than the
gate to source clamp voltage.
(2) VDS = VIN – VO
VDS = 5 V – 3.3 V = 1.7 V
If VIN
≤ 5 V, logic level FET should be considered.
If VIN > 5 V, either logic level or standard MOSFET can be used.
The difference between VIS and VOUT (VDS) must exceed the
voltage drop due to the load current and the on resistance of the
FET. As a safety margin, it is recommended to use a MOSFET
with a VGS at least 1.5 times lower than the calculated VGS value
from Equation 1. Also, in the event the circuit is shorted to
ground, the MOSFET must be able to conduct the maximum
short circuit current. The selected MOSFET must satisfy these
criteria; otherwise, a different pass device should be used. If
the FET data is not available in the catalog, contact the FET
manufacturer.
Thermal Design
The maximum allowable thermal resistance between the FET
junction and the highest ambient temperature must be taken
into account to determine the type of FET package used. One
square inch of PCB copper area as heat sink yields a typical
θJA ~ 60°C/W for the SOT-223 package and θJA ~ 50°C/W for the
SOIC-8 package. For substantially lower thermal resistances,
D
2PAK or TO-220 types of packages are recommended.
For normal applications, the FET can be directly mounted to the
PCB. But, for higher power applications, an external heat sink is
required to satisfy the
θJA requirement and provide adequate heat sink.
Calculating thermal resistance for VIN = 5 V, VO = 3.3 V, and
IO = 3 A:
θ
JA
J
=
×
T–
()
T
VI
AMBMAX
DSMAX
OMAX
TJ = Junction Temperature
TAMBMAX = Maximum Ambient Temperature
VDSMAX = Maximum Drain to Source Voltage
IOMAX = Maximum Output Current
θ
JA
CW
=
×
125
50
17
3
14
.
./
7
For such a low
θ
JA, a P-channel FET from Fairchild, such as the
NDP6020P, in a heat sink mountable TO-220 package, is
required. The required external heat sink is determined as
follows:
θθ
θ
θ
θ
θ
θ
θ
CA
A
C
CA
A
A
A
CA
=−
=− −
=− −
=− −
=
=−
=
JJ
J
J
J
Case to Ambient Thermal Resistance
Junction to Ambient Thermal Resistance
Junction to Case Thermal Resistance
2C W for NDP6020P
14.7 C W
2 C W
12.7 C W
o
oo
o
For a safety margin, select a heat sink with a
θCA less than half
of the value calculated above to allow extended duration of
short circuit. In a natural convection environment, a large heat
sink such as 3" length of Type 63020 extrusion from Aavid Engi-
neering is required.
External Capacitors
The ADP3310 is stable with virtually any good quality capaci-
tors (anyCAP
®), independent of the capacitor’s minimum ESR
(effective series resistance) value. The actual value of the capacitor
and its associated ESR depends on the gm and capacitance of
the external PMOS device. A 10
µF capacitor at the output is
sufficient to ensure stability for up to 10 A output current.
Larger capacitors can be used if high output current surges are
anticipated. Extremely low ESR capacitors (ESR
≈ 0), such as
multilayer ceramic or OSCON, are preferred because they offer
lower ripple on the output. For less demanding requirements,
a standard tantalum or even an aluminum electrolytic is
adequate. However, if an aluminum electrolytic is used, be sure
it meets the temperature requirements because aluminum elec-
trolytic has poor performance over temperature.
Shutdown Mode
Applying a TTL high signal to the EN pin, or tying it to the
input pin, will enable the output. Pulling this pin low or tying it
to ground will disable the output. In shutdown mode, the
controller’s quiescent current is reduced to less than 1
µA.
Gate-to-Source Clamp
An 8 V gate-to-source voltage clamp is provided to protect the
MOSFET in the event the output is suddenly shorted to
ground. This allows the use of the new, low on-state resistance
(RDSON) FETs.
Short Circuit Protection
The power FET is protected during short circuit conditions
with a foldback type of current limiting that significantly reduces
the current.
Current Sense Resistor
Current limit is achieved by setting an appropriate current sense
resistor (RS) across the current limit threshold voltage. Current
limit sense resistor RS is calculated as follows:
R
I
S
O
=
×
005
15
.
(.
)
anyCAP is a registered trademark of Analog Devices, Inc.


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