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ISL5640EVAL Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL5640EVAL Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 11 page 3-10 I/QIN- = +0.5V) and will be at negative full scale when I/QIN+ is equal to VDC - 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient headroom must be provided such that the input voltage never goes above +3V or below AGND. In this case, VDC could range between 0.5V and 2.5V without a significant change in ADC performance. The simplest way to produce VDC is to use the I/QVRIN bias source, I/QVDC, output of the ISL5640. The single ended analog input can be DC coupled (Figure 19) as long as the input is within the analog input common mode voltage range. The resistor, R, in Figure 19 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from I/QIN+ to I/QIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the ISL5640. Operational Mode The ISL5640 contains several operational modes including a normal two channel operation, placing one or both channels in standby and delaying the Q channel data 1/2 clock cycle. The operational mode is selected via the S1 and S2 pins and is asynchronous to either clock. When either channel is placed in standby, the output data is stalled and not high impedance. When recovering from standby, valid data is available after 20 clock cycles. The delay mode can be used to set the Q channel 180 degrees out phase of the I channel if the same clock is driving both channels. If separate, inverted clocks are used for the I and Q channels, this feature can be used to align the data. Sampling Clock Requirements The ISL5640 sampling clock input provides a standard high- speed interface to external TTL/CMOS logic families. In order to ensure rated performance of the ISL5640, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL/CMOS levels. Performance of the ISL5640 will only be guaranteed at conversion rates above 1MSPS (Typ). This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1MSPS must be performed before valid data is available. Supply and Ground Considerations The ISL5640 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the ISL5640 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply can be isolated by a ferrite bead from the digital supply. Refer to the application note “Using Intersil High Speed A/D Converters” (AN9214) for additional considerations when using high speed converters. I/QIN+ I/QIN- ISL5640 VDC R C VIN VDC FIGURE 7. DC COUPLED SINGLE ENDED INPUT OPERATIONAL MODES S1 S2 MODE 0 0 Standby I and Q Channels. 0 1 I channel operates normally with Q Channel in standby mode. 1 0 I and Q Channels operating with I/Q output data in phase. 1 1 I and Q Channels operating with Q data 180 degrees out of phase. ISL5640 |
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