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ADSP-21161N Datasheet(PDF) 2 Page - Analog Devices

No. de pieza ADSP-21161N
Descripción Electrónicos  SHARC Processor
Download  60 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADSP-21161N Datasheet(HTML) 2 Page - Analog Devices

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Rev. C
|
Page 2 of 60
|
January 2013
ADSP-21161N
TABLE OF CONTENTS
Summary ............................................................... 1
General Description ................................................. 3
ADSP-21161N Family Core Architecture .................... 3
ADSP-21161N Memory and I/O Interface Features ....... 5
Development Tools ............................................... 9
Additional Information ........................................ 10
Related Signal Chains .......................................... 10
Pin Function Descriptions ....................................... 11
Boot Modes ....................................................... 16
Specifications ........................................................ 17
Operating Conditions .......................................... 17
Electrical Characteristics ....................................... 18
Package Information ........................................... 19
Absolute Maximum Ratings ................................... 19
ESD Caution ...................................................... 19
Timing Specifications ........................................... 19
Power Dissipation ............................................... 20
Output Drive Currents ......................................... 54
Test Conditions .................................................. 54
Environmental Conditions .................................... 55
225-Ball CSP_BGA Ball Configurations ....................... 56
Outline Dimensions ................................................ 58
Surface-Mount Design .......................................... 58
Ordering Guide ..................................................... 58
REVISION HISTORY
1/13—Rev. B to Rev. C
Updated Development Tools ...................................... 9
Added section, Related Signal Chains .......................... 10
Added footnote 3 to Table 16 in
Memory Read — Bus Master .................................... 27


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