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UPD703100-40 Datasheet(PDF) 86 Page - NEC |
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UPD703100-40 Datasheet(HTML) 86 Page - NEC |
86 / 126 page Preliminary Data Sheet U13995EJ1V0DS00 86 µµµµPD703100-33, 703100-40, 703101-33, 703102-33 (6) DRAM access timing (a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3) Parameter Symbol Condition MIN. MAX. Unit WAIT setup time (to CLKOUT ↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT ↓) <25> tHKW 2ns Data input setup time (to CLKOUT ↑) <26> tSKID 18 ns Data input hold time (from CLKOUT ↑) <27> tHKID 2ns Data output delay time from OE ↑ <37> tDRDOD (0.5 + i) T – 10 ns Row address setup time <56> tASR (0.5 + wRP) T – 10 ns Row address hold time <57> tRAH (0.5 + wRH) T – 10 ns Column address setup time <58> tASC 0.5T – 10 ns Column address hold time <59> tCAH (1.5 + wDA + w) T – 10 ns Read/write cycle time <60> tRC (3 + wRP + wRH + wDA + w) T – 10 ns RAS precharge time <61> tRP (0.5 + wRP) T – 10 ns RAS pulse time <62> tRAS (2.5 + wRH + wDA + w) T – 10 ns RAS hold time <63> tRSH (1.5 + wDA + w) T – 10 ns Column address read time for RAS <64> tRAL (2 + wDA + w) T – 10 ns CAS pulse width <65> tCAS (1 + wDA + w) T – 10 ns CAS-RAS precharge time <66> tCRP (1 + wRP) T – 10 ns CAS hold time <67> tCSH (2 + wRH + wDA + w) T – 10 ns WE setup time <68> tRCS (2 + wRP + wRH) T – 10 ns WE hold time (from RAS ↑) <69> tRRH 0.5T – 10 ns WE hold time (from CAS ↑) <70> tRCH T – 10 ns CAS precharge time <71> tCPN (2 + wRP + wRH) T – 10 ns Output enable access time <72> tOEA (2 + wRP + wRH + wDA + w) T – 28 ns RAS access time <73> tRAC (2 + wRH + wDA + w) T – 28 ns Access time from column address <74> tAA (1.5 + wDA + w) T – 28 ns CAS access time <75> tCAC (1 + wDA + w) T – 28 ns Remarks 1. T = tCYK 2. w: the number of waits due to WAIT. 3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: the number of idle states that are inserted when a write cycle follows a read cycle. |
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