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ST730C12L0L Datasheet(PDF) 2 Page - Vishay Siliconix |
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ST730C12L0L Datasheet(HTML) 2 Page - Vishay Siliconix |
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2 / 9 page  VS-ST730CL Series www.vishay.com Vishay Semiconductors Revision: 15-Apr-14 2 Document Number: 94414 For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS Maximum average on-state current at heatsink temperature IT(AV) 180° conduction, half sine wave double side (single side) cooled 990 (375) A 55 (85) °C Maximum RMS on-state current IT(RMS) DC at 25 °C heatsink temperature double side cooled 2000 A Maximum peak, one-cycle non-repetitive surge current ITSM t = 10 ms No voltage reapplied Sinusoidal half wave, initial TJ = TJ maximum 17 800 t = 8.3 ms 18 700 t = 10 ms 100 % VRRM reapplied 15 000 t = 8.3 ms 15 700 Maximum I2t for fusing I2t t = 10 ms No voltage reapplied 1591 kA2s t = 8.3 ms 1452 t = 10 ms 100 % VRRM reapplied 1125 t = 8.3 ms 1027 Maximum I2 √t for fusing I2 √t t = 0.1 to 10 ms, no voltage reapplied 15 910 kA2 √s Low level value of threshold voltage VT(TO)1 (16.7 % x π x IT(AV) < I < π x IT(AV)), TJ = TJ maximum 0.98 V High level value of threshold voltage VT(TO)2 (I > π x IT(AV)), TJ = TJ maximum 1.12 Low level value of on-state slope resistance rt1 (16.7 % x π x IT(AV) < I < π x IT(AV)), TJ = TJ maximum 0.32 m Ω High level value of on-state slope resistance rt2 (I > π x IT(AV)), TJ = TJ maximum 0.27 Maximum on-state voltage VTM Ipk = 2000 A, TJ = TJ maximum, tp = 10 ms sine pulse 1.62 V Maximum holding current IH TJ = 25 °C, anode supply 12 V resistive load 600 mA Typical latching current IL 1000 SWITCHING PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS Maximum non-repetitive rate of rise of turned-on current dI/dt Gate drive 20 V, 20 Ω, tr ≤ 1 μs TJ = TJ maximum, anode voltage ≤ 80 % VDRM 1000 A/μs Typical delay time td Gate current 1 A, dIg/dt = 1 A/μs Vd = 0.67 % VDRM, TJ = 25 °C 1.0 μs Typical turn-off time tq ITM = 750 A, TJ = TJ maximum, dI/dt = 60 A/μs, VR = 50 V, dV/dt = 20 V/μs, gate 0 V 100 Ω, tp = 500 μs 150 BLOCKING PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS Maximum critical rate of rise of off-state voltage dV/dt TJ = TJ maximum linear to 80 % rated VDRM 500 V/μs Maximum peak reverse and off-state leakage current IRRM, IDRM TJ = TJ maximum, rated VDRM/VRRM applied 80 mA |
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