LMU8UPC50 datasheet(5/7 Pages) LODEV

No. de pieza	LMU8UPC50

Descripción Electrónicos	8 x 8-bit Parallel Multiplier

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Fabricante Electrónico	LODEV [LOGIC Devices Incorporated]

Página de inicio	http://www.logicdevices.com

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5 / 7 page

DEVICES INCORPORATED

LMU08/8U

8 x 8-bit Parallel Multiplier

Multipliers

08/16/2000–LDS.08/8U-R

5

1. Maximum Ratings indicate stress

specifications only. Functional oper-

ation of these products at values beyond

those indicated in the Operating Condi-

tions table is not implied. Exposure to

maximum rating conditions for ex-

tended periods may affect reliability.

2. The products described by this spec-

ification include internal circuitry de-

signed to protect the chip from damag-

ing substrate injection currents and ac-

cumulations of static charge. Neverthe-

less, conventional precautions should

be observed during storage, handling,

and use of these circuits in order to

avoid exposure to excessive electrical

stress values.

3. Thisdeviceprovideshardclampingof

transient undershoot and overshoot. In-

put levels below ground or above VCC

will be clamped beginning at –0.6 V and

VCC

+ 0.6 V. The device can withstand

indefinite operation with inputs in the

range of –0.5 V to +7.0 V. Device opera-

tion will not be adversely affected, how-

ever, input current levels will be well in

excess of 100 mA.

4. Actual test conditions may vary from

those designated but operation is guar-

anteed as specified.

5. Supply current for a given applica-

tion can be accurately approximated by:

where

N = total number of device outputs

C = capacitive load per output

V = supply voltage

F = clock frequency

6. Tested with all outputs changing ev-

ery cycle and no load, at a 5 MHz clock

rate.

7. Tested with all inputs within 0.1 V of

VCC

or Ground, no load.

8. These parameters are guaranteed

but not 100% tested.

NCV F

4

2

NOTES

9. AC specifications are tested with

input transition times less than 3 ns,

output reference levels of 1.5 V (except

tDIS

test), and input levels of nominally

0 to 3.0 V. Output loading may be a

resistive divider which provides for

specified IOH and IOL at an output

voltage of VOH min and VOL max

respectively.

Alternatively, a diode

bridge with upper and lower current

sources of IOH and IOL respectively,

and a balancing voltage of 1.5 V may be

used. Parasitic capacitance is 30 pF

minimum, and may be distributed.

This device has high-speed outputs ca-

pable of large instantaneous current

pulses and fast turn-on/turn-off times.

As a result, care must be exercised in the

testing of this device. The following

measures are recommended:

a. A 0.1 µF ceramic capacitor should be

installed between VCC and Ground

leads as close to the Device Under Test

(DUT) as possible. Similar capacitors

should be installed between device VCC

and the tester common, and device

ground and tester common.

b. Ground and VCC supply planes

must be brought directly to the DUT

socket or contactor fingers.

c. Input voltages should be adjusted to

compensate for inductive ground and VCC

noise to maintain required DUT input

levels relative to the DUT ground pin.

10. Each parameter is shown as a min-

imum or maximum value. Input re-

quirements are specified from the point

of view of the external system driving

the chip. Setup time, for example, is

specified as a minimum since the exter-

nal system must supply at least that

much time to meet the worst-case re-

quirements of all parts. Responses from

the internal circuitry are specified from

the point of view of the device. Output

delay, for example, is specified as a

maximum since worst-case operation of

any device always provides data within

that time.

11. For the tENA test, the transition is

measured to the 1.5 V crossing point

with datasheet loads. For the tDIS test,

the transition is measured to the

±200mV level from the measured

steady-state output voltage with

±10mA loads. The balancing volt-

age, VTH, is set at 3.5 V for Z-to-0

and 0-to-Z tests, and set at 0 V for Z-

to-1 and 1-to-Z tests.

12. These parameters are only tested at

the high temperature extreme, which is

the worst case for leakage current.

S1

IOH

IOL

VTH

CL

DUT

OE

0.2 V

tDIS

tENA

0.2 V

1.5 V

3.5V Vth

1

Z

0

Z

1

Z

0

1.5 V

0V Vth

VOL*

VOH*

VOL*

VOH*

Measured VOL with IOH = –10mA and IOL = 10mA

Measured VOH with IOH = –10mA and IOL = 10mA

FIGURE B. THRESHOLD LEVELS

FIGURE A. OUTPUT LOADING CIRCUIT

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