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MAX1420 Datasheet(PDF) 14 Page - Maxim Integrated Products |
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MAX1420 Datasheet(HTML) 14 Page - Maxim Integrated Products |
14 / 17 page with high-speed op amps. Select the RISO and CIN val- ues to optimize the filter performance, to suit a particu- lar application. For the application in Figure 7, an isolation resistor (RISO) of 50 Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. Connecting CIN from INN to INP may further improve dynamic performance. Using Transformer Coupling An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully dif- ferential signal, required by the MAX1420 for optimum performance. Connecting the center tap of the trans- former to CML provides an AVDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements. In general, the MAX1420 provides better SFDR and THD with fully differential input signals over single-ended input signals, especially for very high input frequencies. In differential input mode, even-order harmonics are sup- pressed and each input requires only half the signal swing compared to single-ended mode. Single-Ended AC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended applica- tion, using a MAX4108 op amp. This configuration pro- vides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. Grounding, Bypassing and Board Layout The MAX1420 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass REFP, REFN, REFIN, and CML with a parallel network of 0.22µF capacitors and 1nF to AGND. AVDD should be bypassed with a similar network of a 10µF bipolar capacitor in parallel with two ceramic capacitors of 1nF and 0.1µF. Follow the same rules to bypass the digital supply DVDD to DGND. Multilayer boards with separate ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arrangement to match the physical location of the analog ground (AGND) and the digital ground (DGND) on the ADCs package. Join the two ground planes at a single point, such that the noisy digital ground currents do not inter- fere with the analog ground plane. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, dig- ital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces and remove digital ground and power planes from under- neath digital outputs. Keep all signal lines short and free of 90 degree turns. 12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420 T1 N.C. VIN 6 1 5 2 4 3 22pF 22pF 1nF 0.1 µF 0.22 µF 25 Ω 25 Ω MINICIRCUITS T1–1T–KK81 INN INP CML 44pF * * * *REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROVE DYNAMIC PERFORMANCE. Figure 8. Using a Transformer for AC-Coupling 14 _____________________________________________________________________________________ |
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Descripción similar - MAX1420 |
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