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74LVT573 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVT573 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 17 page 74LVT573 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 — 22 November 2011 3 of 17 NXP Semiconductors 74LVT573 3.3 V octal D-type transparent latch; 3-state 5. Pinning information 5.1 Pinning Fig 3. Logic diagram mna810 Q4 D4 D LE Q Q3 D3 D LE Q Q2 D2 D LE Q Q1 D1 D LE LE LE Q Q0 D0 D LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 Q LE OE LE LE LE LE Q5 D5 D LE Q LATCH 6 LE Q6 D6 D LE Q LATCH 7 LE Q7 D7 D LE Q LATCH 8 LE (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration for SO20 and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20 74LVT573 OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 001aah713 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aah712 74LVT573 Transparent top view Q7 D6 D7 Q6 D5 Q5 D4 Q4 D3 Q3 D2 Q2 GND(1) D1 Q1 D0 Q0 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area |
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Descripción similar - 74LVT573_15 |
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