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ADC10D1000QML-SP Datasheet(PDF) 1 Page - Texas Instruments |
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ADC10D1000QML-SP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 70 page ADC10D1000QML-SP www.ti.com SNAS466F – FEBRUARY 2009 – REVISED APRIL 2013 ADC10D1000QML Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter Check for Samples: ADC10D1000QML-SP 1 Introduction 1.1 Features 12 • Total Ionizing Dose 100 krad(Si) • Test Patterns at Output for System Debug • Single Event Latch-up 120 Mev-cm2/mg • Programmable 15-Bit Gain and 12-Bit Plus Sign Offset Adjustments • Excellent Accuracy and Dynamic Performance • Option of 1:2 Demuxed or 1:1 Non-demuxed • Low Power Consumption LVDS Outputs • R/W SPI Interface for Extended Control Mode • Auto-sync Feature for Multi-chip Systems • Internally Terminated, Buffered, Differential • Single 1.9V±0.1V Power Supply Analog Inputs • 376 Ceramic Pin Grid Array Package (28.2mm x • Ability to Interleave the 2 Channels to Operate 28.2mm x 3.1mm with 1.27mm ball-pitch) 1 Channel at Twice the Conversion Rate 1.2 Applications • Data Acquisition Systems • Wideband Communications • Direct RF Down Conversion 1.3 Key Specifications (Non-Demux Non-DES Mode, Fs = 1.0 GSPS, • SNR 56.1 dBc (typ) Fin = 248 MHz) • SFDR 63 dBc (typ) • Resolution 10 Bits • Full Power Bandwidth 2.8 GHz (typ) • Conversion Rate • DNL ±0.2 LSB (typ) – Dual channels at 1.0 GSPS (typ) • Power Consumption – Single channel at 2.0 GSPS (typ) – Single Channel Enabled 1.64W (typ) • Code Error Rate 10 −18 (typ) – Dual Channels Enabled 2.9W (typ) • ENOB 9.0 bits (typ) – Power Down Mode 6 mW (typ) 1.4 Description The ADC10D1000 is the latest advance in TI's Ultra-High-Speed ADC family of products. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS in dual channel mode or 2.0 GSPS in single channel mode. The ADC10D1000 achieves excellent accuracy and dynamic performance while consuming a typical 2.9 Watts of power. This space grade, Radiation Tolerant part is rad hard to a single event latch up level of greater than 120MeV and a total dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CPGA package rated over the temperature range of -55°C to +125°C. The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. New features include an auto-sync feature for multi-chip synchronization, independent programmable15- bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the option of two's complement format for the digital output data. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self- 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2009–2013, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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