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ADS5474-SP Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5474-SP Datasheet(HTML) 8 Page - Texas Instruments |
8 / 28 page N CLK D OVR [13:0], N+1 N+5 t CLKL t DRY t DATA t CLKH t a D[13:0], OVR CLK N+2 N+3 N+4 DRY DRY (1) N N+1 N–1 Sample N–1 Latency = 3.5 Clock Cycles ADS5474-SP SLAS574A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com TIMING INFORMATION (1) Polarity of DRY is undetermined. For further information, see the Digital Outputs section. Figure 2. Timing Diagram TIMING CHARACTERISTICS (1) Typical values at TC = +25°C: minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = +125°C, sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3 VPP differential clock, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 200 ps Aperture jitter, rms Internal jitter of the ADC 103 fs Latency 3.5 cycles tCLK Clock period 2.5 50 ns tCLKH Clock pulse duration, high 1 ns tCLKL Clock pulse duration, low 1 ns tDRY CLK to DRY delay(2) Zero crossing, 10-pF parasitic loading to GND on each 700 1600 2500 ps output pin tDATA CLK to DATA/OVR delay(2) Zero crossing, 10-pF parasitic loading to GND on each 650 1600 2600 ps output pin tSKEW DATA to DRY skew tDATA – tDRY, 10-pF parasitic loading to GND on each output -700 0 700 ps pin tRISE DRY/DATA/OVR rise time 10-pF parasitic loading to GND on each output pin 500 ps tFALL DRY/DATA/OVR fall time 10-pF parasitic loading to GND on each output pin 500 ps (1) Timing parameters are assured by characterization, but not production tested. (2) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation delay. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS5474-SP |
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