N

CLK

D

OVR

[13:0],

N+1

N+5

t

CLKL

t

DRY

t

DATA

t

CLKH

t

a

D[13:0], OVR

CLK

N+2

N+3

N+4

DRY

DRY

(1)

N

N+1

N–1

Sample

N–1

Latency = 3.5 Clock Cycles

ADS5474-SP

SLAS574A – SEPTEMBER 2013 – REVISED DECEMBER 2013

www.ti.com

TIMING INFORMATION

(1)

Polarity of DRY is undetermined. For further information, see the Digital Outputs section.

Figure 2. Timing Diagram

TIMING CHARACTERISTICS

(1)

clock, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

200

ps

Aperture jitter, rms

Internal jitter of the ADC

103

fs

Latency

3.5

cycles

Clock period

2.5

50

ns

Clock pulse duration, high

1

ns

Clock pulse duration, low

1

ns

Zero crossing, 10-pF parasitic loading to GND on each

700

1600

2500

ps

output pin

Zero crossing, 10-pF parasitic loading to GND on each

650

1600

2600

ps

output pin

DATA to DRY skew

-700

0

700

ps

pin

DRY/DATA/OVR rise time

10-pF parasitic loading to GND on each output pin

500

ps

DRY/DATA/OVR fall time

10-pF parasitic loading to GND on each output pin

500

ps

(1)

Timing parameters are assured by characterization, but not production tested.

(2)

delay.

8

Submit Documentation Feedback

Copyright © 2013, Texas Instruments Incorporated

Product Folder Links: ADS5474-SP