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MAX5400 Datasheet(PDF) 6 Page - Maxim Integrated Products

No. de pieza MAX5400
Descripción Electrónicos  256-Tap SOT-PoT, Low-Drift Digital Potentiometers in SOT23
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Fabricante Electrónico  MAXIM [Maxim Integrated Products]
Página de inicio  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5400 Datasheet(HTML) 6 Page - Maxim Integrated Products

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256-Tap SOT-PoT,
Low-Drift Digital Potentiometers in SOT23
6
_______________________________________________________________________________________
Detailed Description
The MAX5400/MAX5401 consists of 255 fixed resistors
in series between pins H and L. The potentiometer
wiper (pin W) can be programmed to access any one
of the 256 different tap points on the resistor string. The
MAX5400/MAX5401 uses a 3-wire serial data interface
to control the wiper tap position. This write-only inter-
face contains three inputs: Chip-Select (
CS), Data In
(DIN), and Data Clock (SCLK). When
CS is taken low,
data from the DIN pin is synchronously loaded into the
8-bit serial shift register on the rising edge of each
SCLK pulse. The MSB is shifted in first as shown in
Figure 4. Note that if
CS is not kept low during the entire
data stream, the data will be corrupted and the device
will need to be reloaded. After all 8 data bits have been
loaded into the shift register, they are latched into the
decoder once
CS is taken high. The decoder switches
the potentiometer wiper to the tap position that corre-
sponds to the 8-bit input data. Each resistor cell is
50k
Ω/255 or 196.1Ω for the MAX5400 and 100kΩ/255
or 392.2
Ω for the MAX5401.
The MAX5400/MAX5401 feature power-on reset (POR)
circuitry that sets the wiper to the midscale position at
power-up by loading a binary value of 128 into the 8-bit
latch.
The MAX5400/MAX5401 can be used as a variable
resistor by connecting pin W to either pin H or pin L.
POT REGISTER LOADED
1ST CLOCK PULSE
SCLK
DIN
MSB
LSB
D0
D1
D2
D3
D4
D5
D6
D7
8TH CLOCK PULSE
TIME
CS
Figure 2. Serial Interface Timing Diagram
SCLK
DIN
tCSO
tCSS
tCL
tCH
tDS
tDH
tCP
tCSH
tCS1
tCSW
CS
Figure 3. Detailed Serial Interface Timing Diagram


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