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ADS58J89 Datasheet(PDF) 7 Page - Texas Instruments

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No. de pieza ADS58J89
Descripción Electrónicos  ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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ADS58J89 Datasheet(HTML) 7 Page - Texas Instruments

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ADS58J89
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SBAS659 – NOVEMBER 2014
6.5 Electrical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1-dBFS differential input,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
IAVDD33
3.3-V analog supply current
500
mA
IAVDD18
1.9-V analog supply current
320
mA
IAVDDC
1.8-V clock supply current
18
mA
4-channel SNR boost
472
4-channel decimation filter
323
4-channel burst mode
324
IDVDD
1.8-V digital supply current
mA
2-channel burst mode, 2-channel SNR boost
398
2-channel decimation filter, 2-channel burst mode
324
2-channel decimation filter, 2-channel, discard every
289
other sample
2 lanes per ADC
373
IIOVDD
I/O voltage supply current
mA
1 lane per ADC
185
IPLLVDD
PLL voltage supply current
42
mA
4-channel SNR boost
3.94
4-channel Burst mode
3.67
4-channel decimation filter
3.34
4-channel decimation filter, 1 lane per ADC
3.27
3.5
Pdis
Total power dissipation
W
2-channel SNR Boost, 2-channel burst mode
3.81
2-channel decimation filter, 2-channel burst mode
3.51
2-channel decimation filter, 2-channel, discard every
3.28
other sample
Deep sleep mode power
791
mW
Wake-up time from deep sleep mode
SNR > 60 dB
1.4
ms
Light sleep mode power
1.68
W
Wake-up time from light sleep mode
SNR > 60 dB
8
µs
ANALOG INPUTS
Differential input full-scale
1.0
1.25
1.5
Vpp
Vcm ±
Input common mode voltage
V
50 mV
Input
Differential at DC
1
k
Ω
resistance
Input
Each input to GND
2.75
pF
capacitance
VCM
Common mode voltage output
2.18
V
Analog input bandwidth (–3 dB)
900
MHz
CHANNEL-TO-CHANNEL ISOLATION
Near channel
ƒIN = 170 MHz
85
Crosstalk(1)
dB
Far channel
ƒIN = 170 MHz
95
CLOCK INPUT
Input clock frequency
250
2000(2)
MHz
Input clock amplitude
0.4
1.5
Vpp
Input clock duty cycle
45%
50%
55%
Internal clock biasing
0.9
V
(1)
Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel.
(2)
CLK / 4 mode
Copyright © 2014, Texas Instruments Incorporated
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