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CSD43301Q5M Datasheet(PDF) 7 Page - Texas Instruments

No. de pieza CSD43301Q5M
Descripción Electrónicos  NexFET??Smart Synchronous Rectifier
Download  16 Pages
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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CSD43301Q5M Datasheet(HTML) 7 Page - Texas Instruments

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CSD43301Q5M
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SLPS380B – DECEMBER 2012 – REVISED MAY 2013
Application Information
VDD and Under-Voltage Lockout (UVLO)
The driver IC in the CSD43301Q5M has an internal UVLO protection feature on the VDD pin. Whenever the driver
is in the UVLO condition (i.e. when VDD voltage is less than VON during power up and when VDD voltage is less
than VOFF during power down), this circuit holds the gate of the integrated MOSFET LOW, regardless of the
status of IN and SD. The UVLO is typically 4.2V with 300-mV typical hysteresis. This hysteresis helps prevent
chatter when low VDD supply voltages have noise from the power supply and also when there are droops in the
VDD bias voltage when the system commences switching and there is a sudden increase in IDD. This provides the
capability to operate at low voltage levels (below 5V), along with best-in-class switching characteristics. For
example, at power up, the MOSFET remains OFF until the VDD voltages reaches the UVLO threshold. This
prevents operating the MOSFET in the linear region and conducting a large load current at the same time, which
often results in device overheating and can potentially damage the device.
Since the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, Multi-Layer Ceramic Capacitor (MLCC) bypass capacitors are recommended to prevent noise
problems. A 1 µF MLCC type capacitor should be located as close as possible to the VDD to GND pins of the
gate driver.
Operating Supply Current
The driver IC in the CSD43301Q5M has a low quiescent current in normal operation. IDDQ is less than 0.2 mA
when the device is disabled (SD = 0). The operating current vs. supply voltage is shown in Figure 9, and the
operating current vs. frequency is shown in Figure 10.
Input Stage
The input pins (IN and SD) of the CSD43301Q5M are based on a TTL/CMOS compatible input threshold logic
that is independent of the VDD supply voltage. With a typical high threshold of 2.2 V and a typical low threshold of
1.2 V, the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V
digital power controllers. Wider hysteresis (typical of 0.8 V) offers enhanced noise immunity compared to
traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. These devices also
feature tight control of the input pin threshold voltage levels which eases system design considerations and
ensures stable operation across temperature. The very low input capacitance on these pins reduces loading and
increases switching speed. The device features an important safety function wherein, whenever any of the input
pins are in a floating condition, the output of the respective channel is held in the low state. This is achieved
using a VDD pull-up resistor on the SD input or a GND pull-down resistor on the IN input. This can be seen in the
block diagram in Figure 3.
Power Dissipation
Power Dissipation of the CSD43301Q5M used in secondary rectification is given by the following:
PLOSS = PDRV + PCOND + PSW
(1)
where driver loss is given by
PDRV = VDD × IDD
(2)
and conduction loss is given by
PCOND = I²D_RMS ×RON
(3)
Switching losses consist of body diode conduction losses during dead time, body diode reverse recovery losses,
and output charge losses, given by the following:
PSW = ID × VF × (DTR + DTF) × FSW + QRR × VDRAIN × FSW + ½QOSS × VDRAIN × FSW
(4)
Copyright © 2012–2013, Texas Instruments Incorporated
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