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SM320C6678-HIREL Datasheet(PDF) 11 Page - Texas Instruments |
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SM320C6678-HIREL Datasheet(HTML) 11 Page - Texas Instruments |
11 / 244 page SM320C6678-HIREL SPRS910A—November 2010—Revised August 2013 Copyright 2014 Texas Instruments Incorporated List of Tables 11 Submit Documentation Feedback List of Tables Table 2-1 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2-2 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2-3 Bootloader section in L2 SRAM . . . . . . . . . . . . . . . . 23 Table 2-4 Boot Mode Pins: Boot Device Values . . . . . . . . . . . 25 Table 2-5 Extended Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 2-6 No Boot / EMIF16 Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 2-7 Serial Rapid I/O Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 2-8 Ethernet (SGMII) Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 2-9 PCI Device Configuration Field Descriptions . . . . 27 Table 2-10 BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . 28 Table 2-11 I2C Master Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 2-12 I2C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 2-13 SPI Device Configuration Field Descriptions . . . . 29 Table 2-14 HyperLink Boot Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 2-15 Boot Parameter Table Common Parameters . . . . 31 Table 2-16 EMIF16 Boot Mode Parameter Table . . . . . . . . . . . 31 Table 2-17 SRIO Boot Mode Parameter Table . . . . . . . . . . . . . . 32 Table 2-18 Ethernet Boot Mode Parameter Table . . . . . . . . . . 32 Table 2-19 PCIe Boot Mode Parameter Table . . . . . . . . . . . . . . 34 Table 2-20 I2C Boot Mode Parameter Table. . . . . . . . . . . . . . . . 34 Table 2-21 SPI Boot Mode Parameter Table. . . . . . . . . . . . . . . . 35 Table 2-22 HyperLink Boot Mode Parameter Table . . . . . . . . 36 Table 2-23 DDR3 Boot Parameter Table . . . . . . . . . . . . . . . . . . . 37 Table 2-24 C66x DSP System PLL Configuration . . . . . . . . . . . 38 Table 2-25 I/O Functional Symbol Definitions . . . . . . . . . . . . . 44 Table 2-26 Terminal Functions — Signals and Control by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 2-27 Terminal Functions — Power and Ground. . . . . . 57 Table 2-28 Terminal Functions — By Signal Name . . . . . . . . . 58 Table 2-29 Terminal Functions — By Ball Number . . . . . . . . . 63 Table 3-1 SM320C6678 Device Configuration Pins. . . . . . . . 73 Table 3-2 Device State Control Registers . . . . . . . . . . . . . . . . . 74 Table 3-3 Device Status Register Field Descriptions. . . . . . . 78 Table 3-4 Device Configuration Register (DEVCFG) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 3-5 JTAG ID Register (JTAGID) Field Descriptions . . . 79 Table 3-6 DSP BOOT Address Register (DSP_BOOT_ADDRn) Field Descriptions . . . . . . . . 80 Table 3-7 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions . . . . . . . . . . 81 Table 3-8 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions . . . . . 81 Table 3-9 Reset Status Register (RESET_STAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 3-10 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions . . . . . . . . . . 84 Table 3-11 Boot Complete Register (BOOTCOMPLETE) Field Descriptions. . . . . . . . . . . 85 Table 3-12 Power State Control Register (PWRSTATECTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 3-13 NMI Generation Register (NMIGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 3-14 IPC Generation Registers (IPCGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 3-15 IPC Acknowledgement Registers (IPCARx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table 3-16 IPC Generation Registers (IPCGRH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 3-17 IPC Acknowledgement Register (IPCARH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 3-18 Timer Input Selection Field Description (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 3-19 Timer Output Selection Register (TOUTPSEL) Field Description. . . . . . . . . . . . . . . . . . . 93 Table 3-20 Reset Mux Register (RSTMUXx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 3-21 DSP Suspension Control Register (DSP_SUSP_CTL) Field Descriptions. . . . . . . . . . . . .95 Table 3-22 Device Speed Register (DEVSPEED) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table 3-23 Chip Miscellaneous Control Register (CHIP_MISC_CTL) Field Descriptions . . . . . . . . . . . . 96 Table 4-1 Switch Fabric Connection Matrix Section 1. . . . .101 Table 4-2 Switch Fabric Connection Matrix Section 2. . . . .104 Table 4-3 Switch Fabric Connection Matrix Section 3. . . . .105 Table 5-1 Available Memory Page Protection Schemes . . .113 Table 5-2 CorePac Revision ID Register (MM_REVID) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Table 6-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . .117 Table 6-2 Recommended Operating Conditions . . . . . . . . .118 Table 6-3 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .119 Table 6-4 Power Supply to Peripheral I/O Mapping . . . . . .120 Table 7-1 Power Supply Rails on the SM320C6678 . . . . . . .122 Table 7-2 Core Before IO Power Sequencing . . . . . . . . . . . . .125 Table 7-3 IO Before Core Power Sequencing . . . . . . . . . . . . .127 Table 7-4 Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Table 7-5 SmartReflex 4-Pin VID Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Table 7-6 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Table 7-7 Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Table 7-8 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . .132 Table 7-9 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Table 7-10 Reset Timing Requirements . . . . . . . . . . . . . . . . . . .139 Table 7-11 Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . .139 Table 7-12 Boot Configuration Timing Requirements. . . . . .140 Table 7-13 Main PLL Stabilization, Lock, and Reset Times . .143 Table 7-14 PLL Controller Registers (Including Reset Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 Table 7-15 PLL Secondary Control Register (SECCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 |
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